Headline

Technical Manager | Technical Program Manager | ASIC Physical Design | SEMICON Industry | QuestGlobal | B.Eng(ECE,DCE) | M.Tech(VLSI Design,VIT) | MicroMasters(Business Management,IIMB) | D.B.A(Doctorate,MGNU) | IEEE

About

With over 11 years of experience in the semiconductor industry, I currently serve as a Senior Lead Engineer at Quest Global. My role encompasses program management for the Quest-Marvell account, vertical leadership as the India PD Technical Lead, and horizontal leadership across multiple domain teams such as PD, STA, DFTL, RTL and DV. I am actively contributing to 3nm projects, managing partition and block ownership for RTL to GDS flow, synthesis, and PnR activities, leveraging my expertise in physical design and floorplanning. My professional journey has been marked by hands-on technical contributions and leadership in semiconductor design across leading nodes like 3nm, 5nm, and 7nm. I am proficient in physical design, signoff, and floorplanning, as well as scripting in Tcl, Perl & Python to support project execution. My goal is to deliver innovative solutions that meet complex design challenges while fostering collaboration across teams.

Location

Bengaluru

AI stack

deepseek

gemini

grok

ChatGPT

Glean

Microsoft Copilot

Work experience

Technical Manager, Technical Program Manager at Quest Global, Sep 2026 - Sep 2026 · 1 mo

Senior Lead Engineer, Technical Program Manager at Quest Global, Mar 2024 - Sep 2026 · 2 yrs 7 mos, CW - Marvell - CCDS-PD Roles & Responsibility: Technical Program Manager, Quest-Marvell Account (USA, INDIA, APAC) Horizontal Leadership - Management of All Domain Teams (PD, STA, CLP, Power PTPX, DFT, RTL, Analog, DV) - 150+ Members Vertical Leadership - Overall Global Backend PD Technical Lead (USA, INDIA, APAC) - 80+ Members (12 PD Projects in parallel) USA INDIA - BLR, HYD, Pune, ODC APAC - Vietnam, Malayasia Marvell Partition Lead - Working in 2 projects parallelly + Project Scripting support (Python, TCL & Perl). Project1: (2024 - Present), 3nm Roles & Responsibility: Partition Lead - 40 Blocks, Ownership of 2 Partitions & Blocks PnR + Synthesis, RTL2GDS. Hands on handling 4 blocks in Full Chip TOP. Overview of total 40 blocks and 2 Partitions execution by team members. Project2: (2025 - Present), 3nm Roles & Responsibility: Partition Lead - 5 Blocks, Ownership of 2 Partitions & Blocks PnR + Synthesis, RTL2GDS. Hands on handling 1 Partition and 3 Blocks. Overview of total 22 blocks + 3 Partitions execution by team members. Tools: M1DP* Flow, Innovus, DC compiler, PrimeTime, Calibre, Voltus. CW - Broadcom (2024)

Senior Professional - I, Lead Engineer at Capgemini Engineering, Jan 2023 - Mar 2024 · 1 yr 3 mos, CW - Intel MMG Project: 2023 – 2024 (5 months), Coimbatore, India Client: Intel (5nm); MMG Roles & Responsibilities: Senior Engineer / Lead Engineer, Ownership of Partition PnR, FC flow Handled Partitions: 2, EDA Tools: Fusion Compiler FC, Prime Time PnR Activity: Floorplan, APR PnR, congestion & legality checks, reg2reg/reg2mem/mem2reg timing analysis CW - Intel IPG Project: 2020 – 2023 (3+ years), Penang, Malaysia Client: Intel (10nm, 7nm, 3nm & 5nm); MIG IPG Roles & Responsibilities: Senior Engineer / Lead Engineer, Handled 5-member Team, Daily organizing status collection and overview execution of multiple projects in parallel. • Ownership of Partition PnR, Custom Routes & Signoff, ICC2 flow, FC flow

Professional - II, Project Leader at Capgemini Engineering, Apr 2022 - Dec 2022 · 9 mos, CW - Intel MIG IPG Project: 2020 – 2023 (3+ years), Penang, Malaysia Client: Intel (10nm, 7nm, 3nm & 5nm); MIG IPG Roles & Responsibilities: Senior Engineer / Lead Engineer, Handled 5-member Team, Daily organizing status collection and overview execution of multiple projects in parallel. • Ownership of Partition PnR, Custom Routes & Signoff, ICC2 flow, FC flow

Professional - I, Team Lead at Capgemini Engineering, Oct 2021 - Mar 2022 · 6 mos, CW - Intel MIG Project: 2020 – 2023 (3+ years), Penang, Malaysia Client: Intel (10nm, 7nm, 3nm & 5nm); MIG IPG Roles & Responsibilities: Senior Engineer / Lead Engineer, Handled 5-member Team, Daily organizing status collection and overview execution of multiple projects in parallel. • Ownership of Partition PnR, Custom Routes & Signoff, ICC2 flow, FC flow

Associate Consultant at Altran, Oct 2019 - Sep 2021 · 2 yrs, Penang, Malaysia, CW - Intel MIG Project: 2020 – 2023 (3+ years), Penang, Malaysia Client: Intel (10nm, 7nm, 3nm & 5nm); MIG IPG Roles & Responsibilities: Senior Engineer / Lead Engineer, Handled 5-member Team. • Ownership of Partition PnR, Custom Routes & Signoff, ICC2 flow, FC flow CW - Intel PSG Project: 2019 – 2020 (5 months), Penang, Malaysia Client: Intel (10+++nm); PSG Roles & Responsibilities: Senior Engineer, Handled 2 Partitions, Signoff Activity, ICC2 PnR flow, Client On-site • Signoff Activity: PT Hold ECO fix scripts, Timing analyse & closure, LV DRC shorts opens fix. Altran was acquired by Capgemini

VLSI Engineer, Team Sub Lead at SmartPlay Technologies - An Aricent Company, Dec 2017 - Oct 2019 · 1 yr 11 mos, Chennai, Tamil Nadu, India, CW - Intel HPG Project: 2019 (1 year), Coimbatore, India Client: Intel (10+++nm); SDG HPG Roles & Responsibilities: Team Lead, handled 5 members to 30 members Team in ODC, Handled 3 Partitions, ICC2 PnR flow. Overview of 75 blocks assignment and execution. • PnR Activity: Floor Plan Automation, Path Grouping, Bound Creation, Placement and Timing Analysis CWF - Qualcomm SOC HW - Engineer II Project: 2018 – 2019 (1+ years), Chennai, India Client: Qualcomm (28nm); SOC-HW Roles & Responsibilities: Engineer-II (Senior Engineer), Two Projects in 28nm, ICC2 PnR flow • PnR, STA, DFT Aricent was acquired by Altran

Physical Design Engineer at Graphene Semiconductor Services Private Limited, Mar 2017 - Nov 2017 · 9 mos, Bengaluru, Karnataka, India, CW - Intel SDG, WWID: 11742724 Client: Intel (10nm); SDG Roles & Responsibilities: Engineer, Handled 1 Super partition + 2 partitions, SoC 10nm Project, ICC2 PnR flow. • PnR Activity Graphene Semiconductor Services Pvt. Ltd was acquired by L&T Technology Services Ltd Limited on October 15, 2018

Education

Master of Technology (M.Tech.), VLSI DESIGN, Vellore Institute of Technology

Doctor of Business Administration - DBA, GlobalNxt University