Headline

Analog/Custom Layout Engineer

About

Analog/Custom Layout Engineer with 5+ years of experience in semiconductor design, specializing in LPDDR and DDR memory interfaces, high-speed interface layout, advanced-node implementation, EM/IR signoff, physical verification, and reliability-driven layout optimization. Key Skills: • Tools: Cadence Virtuoso, Pegasus, VoltusFi, Iquantus, ParagonX, Calibre, ICV • Layout: Matching, Shielding, Floorplanning, Placement, Routing, Block Integration, Layout Optimization, ECO Implementation • Analysis: EM/IR, RC Extraction, Signal Integrity, Latchup, Antenna, Density, LVS/DRC Closure • Advanced Technology Nodes: 28nm, 7nm, 5nm, 3nm, 18A, 14A • Domains: Analog Layout, Custom Layout, Mixed-Signal Layout, High-Speed IO, Memory Interfaces, Semiconductor Design. • Methodologies: AI-assisted Design Workflows, Real-time Resistance/Current Estimation Concepts Academic Achievements: 1. Presented a paper on "Design of a Constant Bandwidth Variable Gain Amplifier for 5G receivers" at the "International Conference on Advances in Communications, Computing and Embedded Systems (ACCES)-2020." 2. Accepted for publication in "International Journal of Systems, Control and Communications (IJSCC)" by Inderscience Publishers. Passionate about advanced semiconductor technologies, high-speed memory systems, AI/HPC infrastructure, and next-generation silicon solutions.

Location

Hyderabad

AI stack

claude

gemini

github copilot

grok

kimi

githubcopilot

Work experience

Design Engineer II at Cadence Design Systems, Jul 2024 - Present · 2 yrs 3 mos, Hyderabad, Telangana, India

Analog Layout Engineer at Capgemini Engineering, Sep 2021 - Jul 2024 · 2 yrs 11 mos, Bengaluru, Karnataka, India

Analog Layout Trainee at VLSIGuru Training Institute, Mar 2021 - Sep 2021 · 7 mos, Bengaluru, Karnataka, India, • Designing the Phase-Locked Loop using 28nm technology Description: Developing Phase-locked loop or PLL layout and schematic using Synopsys Custom Compiler tool. Also checking and resolving the DRC and LVS errors. And Optimizing the layout by performing sharing of devices, floor-planning, placement and routing. • Designing the Operational Amplifier using 28nm technology Description: Developed layout and schematic using Synopsys Custom Compiler tool and cleaned DRC and LVS. Meeting the matching technique for critical devices like differential pair and current mirror. Maintain metal width according to the current rating and all critical nets should have same parasitic. • Designing the D-Flip Flop using 28nm technology Description: Developed layout and schematic using Synopsys Custom Compiler tool and cleaned DRC and LVS. Optimized the layout with floor-planning, Clock signal is considered as the critical signal and routing has been done in consideration of timing constraint of the critical signal. • Designing the standard cells using 28nm technology Description: Developed layout and schematic of INVERTER, NAND, NOR, AND, OR, XOR, XNOR using Synopsys Custom Compiler tool and cleaned DRC and LVS.

Education

Master of Technology - MTech, VLSI DESIGN, SRM IST Chennai

Bachelor of Engineering (BE), Electrical and Electronics Engineering, gyan ganga institute of technology and sciences