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Yashvanthini Selvam

ECE Student @ Sathyabama Institute of Science & Technology, Chennai | Aspiring RTL Design Engineer | Verilog HDL | ASIC Frontend Design | Digital Design | Cadence Xcelium

Greater Chennai Area

Education

Sathyabama Institute of Science & Technology, Chennai

Bachelor of Engineering, Electrical, Electronics and Communications Engineering

Sathyabama Institute of Science & Technology, Chennai

20224 yrs2026

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Headline

ECE Student @ Sathyabama Institute of Science & Technology, Chennai | Aspiring RTL Design Engineer | Verilog HDL | ASIC Frontend Design | Digital Design | Cadence Xcelium

About

Electronics and Communication Engineering student specializing in RTL Design and Frontend VLSI Design. Skilled in Verilog HDL, FSM Design, Digital Logic Design, and Timing Concepts with hands-on experience in designing and simulating hardware modules. Developed multiple RTL projects including Synchronous FIFO, AMBA APB Protocol, and UART Communication Protocol using Verilog. Experienced in waveform analysis, testbench development, and debugging using Cadence Xcelium and ModelSim. Actively seeking Internship or Entry-Level opportunities in RTL Design, ASIC Frontend Design, FPGA Design, and Digital IC Design where I can contribute to high-performance semiconductor systems and continue building strong VLSI expertise.

Location

Greater Chennai Area

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, Sathyabama Institute of Science & Technology, Chennai

Yashvanthini Selvam - ECE Student @ Sathyabama Institute of Science & Technology, Chennai | Aspiring RTL Design Engineer | Verilog HDL | ASIC Frontend Design | Digital Design | Cadence Xcelium in Greater Chennai Area | Tal