---
title: "Vishwas Deshpande - Staff Engineer in Bengaluru | Tal"
description: "Meet Vishwas Deshpande, Senior SoC Design Engineer at Intel India Pvt Ltd based in Bengaluru. AI stack includes claude and github copilot."
image: "https://tal.club/meet/vishwas-deshpande/share-image"
---

# Vishwas Deshpande on Tal

## Headline

Senior SoC Design Engineer at Intel India Pvt Ltd

## About

I am an accomplished professional delivering over 14 years of career success in VLSI, Digital Design, and ASIC Design Flow, seeking a challenging Tech Lead role in the field of VLSI Design Flow and ASIC Design Flow\. My dexterity lies in VLSI and Digital Design, demonstrating profound mastery in Design Flow, Design Implementation, Design Automation, Synthesis, Static Timing Analysis, and SoC Design across diverse industries\. Over the time, I have proved my excellence in crafting and engineering cutting\-edge digital design subsystems, from inception to successful tape\-out, further affirming an illustrious and distinguished track record in the realm of digital design\.

## Location

Bengaluru

## AI stack

claude

github copilot

## Work experience

Staff Engineer at Analog Devices, Feb 2025 \- Present · 1 y 7 mo, Bangalore

Senior Member Technical Staff at Mirafra Technologies, May 2023 \- Jan 2025 · 1 y 8 mo, Google Bangalore

Senior SoC Design Engineer at Intel India Pvt Ltd at Intel Corporation, Jun 2018 \- Feb 2023 · 4 y 8 mo, Bengaluru, Karnataka, India, Actively involved in Design QA and RTL quality signoff for PCIE subsystem and SoC for Intel's 10th, 12th and 13th Generation Intel Core Processors

Senior ASIC Digital Design Engineer at Synopsys Ind pvt ltd, Jul 2016 \- May 2018 · 1 yr 11 mos, Hyderabad Area, India, Design flow on high\-speed SERDES based designs including Logic Synthesis, Lint checks, CDC checks, DFT insertion, Formal Verification\.

Digital Design Engineer at Texas Instruments, Jan 2014 \- Dec 2015 · 2 yrs, Bengaluru Area, India, Digital Design Flow on ARM Cortex M0\+ based microcontrollers including Logic Synthesis, Lint, CDC, Formal Verification, Static Timing Analysis and timing closure\.

Automation Lead at Texas Instruments, Jan 2013 \- Jun 2016 · 3 yrs 6 mos, Bengaluru Area, India, Automating RTL code generation, testbenches and verification scripts Automating android device driver codes

Senior Software Engineer at National Semiconductor, Oct 2007 \- Dec 2012 · 5 yrs 3 mos, Bengaluru Area, India, Validation and deployment of digital design tools to the design teams\. Devising methodologies and coming up with new utilities for the digital teams\. Utility development for I2C and SPI communication protocols\.

System Engineer at IBM, 2005 \- 2007 · 2 yrs

## Education

GMITE, General Management, Indian Institute of Management Bangalore

Master of Technology \(M\.Tech\.\), Microelectronics, National Institute of Technology Karnataka

[View the original profile](https://tal.club/meet/vishwas-deshpande)

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