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VISHAL SAINI

Associate Staff Engineer @ Samsung Semiconductor

Bengaluru

2+ years of work experience

Samsung Semiconductor
Mar 20266 mosPresent

Samsung Semiconductor
Aug 20241 yr 8 mosMar 2026

Bengaluru, Karnataka, India

​Developed a comprehensive IEEE 1500-compliant vendor verification environment for CHBM memory modules. ​Architected and implemented core UVM-based components, including a custom Driver, Monitor, and Scoreboard, to validate the Core Test (CTEST) functionality. ​Developed a robust Checker and Scoreboard logic to ensure data integrity between the IEEE 1500 wrapper and the memory core. ​Defined and analyzed functional coverage to ensure 100% verification of the test access mechanism (TAM) and instruction registers.
Samsung Semiconductor
Jan 20247 mosJul 2024

Bengaluru, Karnataka, India

Hands-on experience with UVM and SystemVerilog for digital design verification, successfully verifying I2C protocol compliance and asynchronous FIFO functionality, developing comprehensive verification plans and collaborating with design teams to resolve issues and improve design quality.

VISHAL’s AI Stack

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Education

National Institute of Technology Karnataka

M.Tech, VLSI Design

National Institute of Technology Karnataka

20222 yrs2024
Kamla Nehru Institute of Technology, Sultanpur

B.Tech, ELECTRICAL ENGINEERING

Kamla Nehru Institute of Technology, Sultanpur

20184 yrs2022

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Headline

Associate Staff Engineer @ Samsung Semiconductor

About

Verification Engineer with UVM and SystemVerilog expertise, developing efficient testbenches and verifying complex digital designs.

Location

Bengaluru

AI stack

antigravity

opencode

Work experience

Associate Staff Engineer at Samsung Semiconductor, Mar 2026 - Present · 6 mos

Senior Engineer at Samsung Semiconductor, Aug 2024 - Mar 2026 · 1 yr 8 mos, Bengaluru, Karnataka, India, ​Developed a comprehensive IEEE 1500-compliant vendor verification environment for CHBM memory modules. ​Architected and implemented core UVM-based components, including a custom Driver, Monitor, and Scoreboard, to validate the Core Test (CTEST) functionality. ​Developed a robust Checker and Scoreboard logic to ensure data integrity between the IEEE 1500 wrapper and the memory core. ​Defined and analyzed functional coverage to ensure 100% verification of the test access mechanism (TAM) and instruction registers.

Assistant Engineer at Samsung Semiconductor, Jan 2024 - Jul 2024 · 7 mos, Bengaluru, Karnataka, India, Hands-on experience with UVM and SystemVerilog for digital design verification, successfully verifying I2C protocol compliance and asynchronous FIFO functionality, developing comprehensive verification plans and collaborating with design teams to resolve issues and improve design quality.

Education

M.Tech, VLSI Design, National Institute of Technology Karnataka

B.Tech, ELECTRICAL ENGINEERING, Kamla Nehru Institute of Technology, Sultanpur

VISHAL SAINI - Associate Staff Engineer in Bengaluru | Tal