Headline

Principal Engineer | Ex Meta | Ex Intel | Ex Intel Labs | Ex Qualcomm | IIT Alumnus | TAMU Aggie

About

• Self-driven Engineer with 15+ years of hands-on experience leading RTL and system integration, FPGA bring-up, data-center systems prototyping, and validation. • Extensive experience in HAPS prototyping, emulation, firmware and embedded system bring-up for various platforms, driving projects from concept through to real deployment. • Adept at resolving technical challenges in high-pressure environments, with a proven track record of building and validating custom hardware-software systems in fast-paced development cycles. • Leader in a highly productive and innovative team that works closely with key product teams in SoC Prototype development and software development. • Key member of commercially successful chip designs: Intel Core i3/i5/i7, XEON Gen 5 & 6, Qualcomm SoC MSM Family, Infineon Baseband SoC, Intel 3G & 4G SoC, Google Glass SoC • Highly motivated, innovative and tenacious individual. • Demonstrated measurable track records of experiences and accomplishments. • Actively contributing to the ongoing research projects. Specialties: SoC/ASIC/System Prototyping and Emulation, Platform Architecture, Embedded Software, SoC Bring Up, Validation, Physical layer communication systems design, OFDM & OFDMA, channel coding for communications, computer networks -- wireless LANs.

Location

San Francisco Bay Area

Work experience

Principal Engineer at Cadence, Nov 2025 - Present · 8 mos, On-site

FPGA & Emulation Engineer at Meta, Oct 2024 - Nov 2025 · 1 yr 2 mos, On-site, • Deliver emulation and prototyping models from RTL on X2, Zebu and Palladium • Drive FPGA methodologies for HW verification and SW development. • Develop tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW teams during debug, runtime, and data analysis from emulation • Integrate Job Scheduler features for large scale queue-based interface to dispatch FPGA and emulation jobs supporting prioritization and job starvation mitigation for 200+ users. • Partner with vendors to debug issues and deploy new capabilities.

Tech. Lead & Customer engagement (FPGA & Emulation) at Intel Corporation, Jan 2018 - Nov 2024 · 6 yrs 11 mos, San Francisco Bay Area, • Led hands-on bring-up of VCS/FPGA/ZSE Xeon Emulation models, conducting functional validation of reset flows involving firmware and software stacks. Personally identified and debugged RTL, BIOS, and ROM issues using lab tools. • Directly engaged with external customers on interop projects, enabling new security flows on Silicon and HAPS FPGAs. Used tools like PCIe Analyzer and Lauterbach Trace32 to resolve issues and successfully cut time-to-market by two quarters. • Executed the HAPS FPGA bring-up of Intel Data Center GPU SoC for AI and HPC applications, ensuring proper functionality and meeting performance benchmarks for US Federal Projects. • Developed and validated Server SoC HAPS FPGA prototypes focused on CXL/PCIe IP by handling timing constraints, synthesis, routing, and creating debug scripts for key interfaces like JTAG, PCIe, UART, I2C, SPI. • Designed and implemented a FPGA Cloud Usage that boosted scalability and model convergence by 25%, significantly improving adoption rates across customer platforms. • Actively performed synthetic validation of IPs such as Power Management, Secure Boot, and DMA before release, ensuring system stability and readiness for customer deployment. • Led a multi-disciplinary team of 10+ engineers and technicians, managing the transition to Xilinx HAPS FPGAs for critical SoC development. Coordinated hands-on integration tasks across geographies, ensuring alignment with SoC milestones. • Worked closely with program managers and device integration teams to drive milestones for DSPs, sensors, and RF systems, including use cases for 3G UMTS, 4G LTE, GPS, Wi-Fi, and Bluetooth in complex embedded environments. • Chaired two cross-organizational forums, facilitating collaboration between teams (CAD, IPs, Validation, SW) and driving FPGA-based use cases and validation flows, with 15+ active participants from different departments • Consistently recognized as a top performer, receiving multiple divisional and cross-department awards

Tech. Lead, Data Center Software & Solutions Group at Intel Corporation, Jan 2016 - Dec 2017 · 2 yrs, California, United States, • Led a task-force of 4 engineers in the hands-on development of accelerator IP targeting Big Data workloads on Data Center products. This involved implementing the Xeon+FPGA flow, where I personally oversaw the simulation and bring-up of custom IP cores for cloud deployment at a leading CSP customer. • Directly collaborated with the Data Center team to optimize platform acceleration for Big Data, focusing on improving system throughput and performance for real-time analytics. • Co-developed a Gzip compression IP as a hardware accelerator, actively involved in RTL simulation, debugging, and FPGA validation. This IP was successfully deployed by a major CSP to enhance data compression and processing efficiency. • Executed hands-on RTL simulation and FPGA bring-up for a Java Byte-code Processor, designed specifically for Big Data applications. This included managing the end-to-end development of the processor, validating its integration into the FPGA-based environment to accelerate data center workloads.

Research Scientist at Intel Labs, Jan 2014 - Dec 2015 · 2 yrs, San Francisco Bay Area, Micro Architecture Lab • Core member of ADR Team (Advanced Design Research) • Investigate the feasibility of applying concepts to potential inventions and products typically 7+ years prior to landing on a product roadmap. • Power/area/performance driven architecture and microarchitecture optimization of CPU, GPU, interconnect fabric and SoC platform architecture. • FPGA emulation and prototyping of key design IP and SoC

Staff Engineer at Infineon Mobile Communications, Jan 2010 - Dec 2013 · 4 yrs, San Francisco Bay Area, • Key member of 5+ commercially successful wireless chip designs • Pro-active staff member of Architecture and Emulation Team focusing on Bluetooth Core • Lead SoC FPGA Development for Intel’s first Connectivity (BT/WLAN/FM/GNSS) • Managed a complex portfolio of FPGA/Firmware release program • Test Plan Development and Execution, Pre Silicon FPGA/Firmware Development • Designed ROM Patching, External Memory I/F, PCM, USIM Controller, IC USB • Silicon Bring up/Characterization/Power/Coexistence etc.

Education

MS, Electrical Engineering, Texas A&M University

B. Tech., Electrical Engineering, Indian Institute of Technology, Bombay