---
title: "Vishakh Venugopal - Senior Lead Engineer in Bangalore Urban | Tal"
description: "Meet Vishakh Venugopal, Senior Lead Engineer at Qualcomm based in Bangalore Urban. AI stack includes claude code, gemini, and github copilot. Explore public work links including github."
image: "https://tal.club/meet/vishakh-venugopal/share-image"
---

# Vishakh Venugopal on Tal

## Headline

Senior Lead Engineer at Qualcomm

## About

A passionate VLSI professional with 6 years of industry experience, specializing in the verification and validation of complex SoC designs\. I hold a Master’s degree in VLSI Design from NITK Surathkal, where I built a strong foundation in digital design and verification, complemented by a year\-long internship at Intel as a Graduate Technical Intern\. Currently, I work at Qualcomm, where I focus on post\-silicon debug support for Snapdragon CPUs, scandump collection and decoding, automation of debug flows and development of debug infrastructure\. Over the past 5 years in AMD, I have gained strong expertise in the verification of non\-scan features such as JTAG, clocking, and MBIST, enabling me to contribute to the robustness and reliability of advanced SoC architectures\. I am deeply motivated by solving complex verification challenges and accelerating debug workflows through automation\. As an advanced\-level Python programmer, I leverage object\-oriented design principles to develop efficient and scalable solutions for diverse problems\. I am also proficient with industry\-standard debug tools like Verdi, which strengthen my ability to analyze, isolate, and resolve issues effectively\.

## Location

Bangalore Urban

## AI stack

claude code

gemini

github copilot

notebooklm

githubcopilot

Microsoft Copilot

## Work experience

Senior Lead Engineer at Qualcomm, Jun 2025 \- Present · 1 yr 3 mos, Bengaluru, Karnataka, India, Working on CPU debug infrastructure development for Snapdragon SoCs Responsible for scandump validation, analysis, and decoding across all CPU targets Supporting internal teams with scandump collection, interpretation, and debug assistance\. Cross team interactions with DFT, DV and CAD\.

Sr\. Silicon Design Engineer at AMD, Sep 2022 \- Jun 2025 · 2 yrs 10 mos, Bengaluru, Karnataka, India, Owned SoC\-level MBIST verification for multiple server\-class SoCs, ensuring robust test coverage and silicon readiness Experience with JTAG, clocking architectures, and IEEE 1687 \(IJTAG\) features and validation Proficient in Perl, Python, CSH, and C\+\+ for automation, scripting, and verification flow optimization Supported silicon bring\-up, ATE pattern delivery, and post\-silicon debug activities Developed automation to optimize test patterns and reduce bring\-up cycle time Collaborated with cross\-functional, multi\-site global teams

Design Engineer 2 at AMD, Jun 2019 \- Sep 2022 · 3 yrs 4 mos, Bengaluru, Karnataka, India, A part of the AMD Server SOC DFT verifcation team and successfully contributed to development of 3 generations of SOCs\.

Intern at Intel Corporation, Jun 2018 \- May 2019 · 1 yr, Bangalore, Worked in the Platform Development team, implementing the DFT MBIST architecture for 14nm and 22nm memory IPs, with focus on automation of the flows using Perl and shell scripts\.

## Education

Master of Technology \- MTech, VLSI Design, National Institute of Technology Karnataka

Bachelor of Technology \- BTech, Electrical, Electronics and Communications Engineering, College of Engineering Trivandrum

## Public links

- github: https://github\.com/vishakh567

[View the original profile](https://tal.club/meet/vishakh-venugopal)

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