---
title: "Vipul Sunil Kotkar - Analog Layout Trainee | Tal"
description: "Meet Vipul Sunil Kotkar, Analog Layout Trainee at Takshila Institute of VLSI Technologies. AI stack includes hugging face, ollama, and openai. Explore public work links including github."
image: "https://tal.club/meet/vipul-sunil-kotkar/share-image"
---

# Vipul Sunil Kotkar on Tal

## AI stack

hugging face

ollama

openai

replit

## Work experience

Analog Layout Trainee at Takshila Institute of VLSI Technologies, Mar 2026 \- Present · 2 mos, Bengaluru, I had the opportunity to enhance my skills in custom IC layout and verification during my training\. • Engaged in hands\-on projects utilizing Cadence Virtuoso for custom IC layout design\. • Applied matching techniques and parasitic\-aware design concepts to improve layout quality\. • Conducted DRC/LVS, gaining insights into the layout verification and sign\-off flow\.

Analog/Mixed\-Signal Layout Engineer at Nuvionx Ltd, Jan 2025 \- Jan 2026 · 1 yr 1 mo, Newcastle Upon Tyne, Designed and verified hardware blocks for medical\-grade ICs including patient vital monitors and infusion pumps, with strict attention to signal integrity and timing constraints Implemented interface controller circuits \(SPI/I2C\) and FIFO\-based buffering blocks, applying layout\-aware design principles to ensure deterministic data transfer Developed safety\-critical hardware logic including threshold comparators and fault\-state detection circuits — directly transferable to analog protection and bias circuits in IC layout Performed functional simulation and hardware validation, debugging signal integrity and timing issues using Vivado and on\-board analysis tools

Postgraduate Researcher — Microsystem Research Group at Newcastle University, Mar 2024 \- Jan 2025 · 11 mos, Newcastle Upon Tyne, Researched low\-power analog architectures including LDOs, Self\-Timed Circuits, and elastic pipelines for energy\-efficient SoC computing — building deep understanding of analog block design and layout constraints Designed and validated energy\-harvesting modules with configurable capacitive banking, applying layout\-driven design techniques for ultra\-low\-power operation Performed physical design analysis of asynchronous SoC modules, including waveform debugging and timing analysis using Cadence Virtuoso Studied GALS architectures and clock domain crossing — critical knowledge for mixed\-signal layout floorplanning

Shift Manager at McDonald's, Jan 2023 \- Nov 2025 · 2 yrs 11 mos, Gateshead

Automation Engineer intern at Tru Engineering and works, Jan 2022 \- Jun 2022 · 6 mos, India, Developed Python\-based test automation for embedded systems, achieving a 25% reduction in manual verification effort\. Created and executed QA test plans, enhancing functional coverage by 10% across product releases\. Supported testbench validation, fault diagnosis, and regression testing for embedded control boards, ensuring product reliability\.

## Education

Master of Science \- MS, Microelectronics, Newcastle University

Bachelor of Engineering \- BE, Electronics and Communications Engineering, Savitribai Phule Pune University

## Public links

- github: https://github\.com/vipul\-kotkar

[View the original profile](https://tal.club/meet/vipul-sunil-kotkar)

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