Vipul Sunil Kotkar profile photo 1 on Tal

Vipul Sunil Kotkar

4+ years of work experience

Takshila Institute of VLSI Technologies
Mar 20262 mosPresent

Bengaluru

I had the opportunity to enhance my skills in custom IC layout and verification during my training. • Engaged in hands-on projects utilizing Cadence Virtuoso for custom IC layout design. • Applied matching techniques and parasitic-aware design concepts to improve layout quality. • Conducted DRC/LVS, gaining insights into the layout verification and sign-off flow.
Jan 20251 yr 1 moJan 2026

Newcastle Upon Tyne

Designed and verified hardware blocks for medical-grade ICs including patient vital monitors and infusion pumps, with strict attention to signal integrity and timing constraints Implemented interface controller circuits (SPI/I2C) and FIFO-based buffering blocks, applying layout-aware design principles to ensure deterministic data transfer Developed safety-critical hardware logic including threshold comparators and fault-state detection circuits — directly transferable to analog protection and bias circuits in IC layout Performed functional simulation and hardware validation, debugging signal integrity and timing issues using Vivado and on-board analysis tools
Newcastle University
Mar 202411 mosJan 2025

Newcastle Upon Tyne

Researched low-power analog architectures including LDOs, Self-Timed Circuits, and elastic pipelines for energy-efficient SoC computing — building deep understanding of analog block design and layout constraints Designed and validated energy-harvesting modules with configurable capacitive banking, applying layout-driven design techniques for ultra-low-power operation Performed physical design analysis of asynchronous SoC modules, including waveform debugging and timing analysis using Cadence Virtuoso Studied GALS architectures and clock domain crossing — critical knowledge for mixed-signal layout floorplanning
McDonald's
Jan 20232 yrs 11 mosNov 2025

Gateshead

Jan 20226 mosJun 2022

India

Developed Python-based test automation for embedded systems, achieving a 25% reduction in manual verification effort. Created and executed QA test plans, enhancing functional coverage by 10% across product releases. Supported testbench validation, fault diagnosis, and regression testing for embedded control boards, ensuring product reliability.
GitHub
@vipul-kotkar

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Education

Newcastle University

Master of Science - MS, Microelectronics

Newcastle University

20221 yr2023
Savitribai Phule Pune University

Bachelor of Engineering - BE, Electronics and Communications Engineering

Savitribai Phule Pune University

20174 yrs2021

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AI stack

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Work experience

Analog Layout Trainee at Takshila Institute of VLSI Technologies, Mar 2026 - Present · 2 mos, Bengaluru, I had the opportunity to enhance my skills in custom IC layout and verification during my training. • Engaged in hands-on projects utilizing Cadence Virtuoso for custom IC layout design. • Applied matching techniques and parasitic-aware design concepts to improve layout quality. • Conducted DRC/LVS, gaining insights into the layout verification and sign-off flow.

Analog/Mixed-Signal Layout Engineer at Nuvionx Ltd, Jan 2025 - Jan 2026 · 1 yr 1 mo, Newcastle Upon Tyne, Designed and verified hardware blocks for medical-grade ICs including patient vital monitors and infusion pumps, with strict attention to signal integrity and timing constraints Implemented interface controller circuits (SPI/I2C) and FIFO-based buffering blocks, applying layout-aware design principles to ensure deterministic data transfer Developed safety-critical hardware logic including threshold comparators and fault-state detection circuits — directly transferable to analog protection and bias circuits in IC layout Performed functional simulation and hardware validation, debugging signal integrity and timing issues using Vivado and on-board analysis tools

Postgraduate Researcher — Microsystem Research Group at Newcastle University, Mar 2024 - Jan 2025 · 11 mos, Newcastle Upon Tyne, Researched low-power analog architectures including LDOs, Self-Timed Circuits, and elastic pipelines for energy-efficient SoC computing — building deep understanding of analog block design and layout constraints Designed and validated energy-harvesting modules with configurable capacitive banking, applying layout-driven design techniques for ultra-low-power operation Performed physical design analysis of asynchronous SoC modules, including waveform debugging and timing analysis using Cadence Virtuoso Studied GALS architectures and clock domain crossing — critical knowledge for mixed-signal layout floorplanning

Shift Manager at McDonald's, Jan 2023 - Nov 2025 · 2 yrs 11 mos, Gateshead

Automation Engineer intern at Tru Engineering and works, Jan 2022 - Jun 2022 · 6 mos, India, Developed Python-based test automation for embedded systems, achieving a 25% reduction in manual verification effort. Created and executed QA test plans, enhancing functional coverage by 10% across product releases. Supported testbench validation, fault diagnosis, and regression testing for embedded control boards, ensuring product reliability.

Education

Master of Science - MS, Microelectronics, Newcastle University

Bachelor of Engineering - BE, Electronics and Communications Engineering, Savitribai Phule Pune University

Public links

github: https://github.com/vipul-kotkar

Vipul Sunil Kotkar - Analog Layout Trainee | Tal