---
title: "VIMLESH KUMAR - Principal Design Engineer in Bengaluru | Tal"
description: "Meet VIMLESH KUMAR, Physical Design Engineer at NXP Semiconductor based in Bengaluru. AI stack includes claude code."
image: "https://tal.club/meet/vimlesh-kumar-2/share-image"
---

# VIMLESH KUMAR on Tal

## Headline

Physical Design Engineer at NXP Semiconductor

## Location

Bengaluru

## AI stack

claude code

## Work experience

Principal Design Engineer at NXP Semiconductors, Apr 2026 \- Present · 6 mos

Senior Lead Engineer at NXP Semiconductors, Jun 2021 \- Apr 2026 · 4 yrs 11 mos, India

Physical Design Engineer at Intel Corporation, Mar 2020 \- Jun 2021 · 1 yr 4 mos, Bengaluru, Karnataka, India, Ownership of block level PnR from RTL to GDS\. Worked on signoff STA, Physical Verification using Calibre, EMIR using Redhawk

Senior Physical Design Engineer at Si2chip Technologies Pvt\. Ltd\., Apr 2017 \- Mar 2020 · 3 yrs, Bengaluru, Karnataka, India, Ownership of block level PnR from RTL till GDS\. Worked in Qualcomm and Samsung projects and completed tapeouts of complex blocks with high frequency feedthroughs\.

Physical Design Engineer at Intel Corporation, Sep 2015 \- Apr 2017 · 1 yr 8 mos, Bengaluru Area, India, Worked on integrated GPU blocks based on 10nm and 14nm technology node\. I was responsible for achieving signoff quality of GDS by working on PnR, Physical Verification, signoff STA and PDN\.

Field Application Engineer at Trident Techlabs Pvt\. Ltd\., Dec 2014 \- Aug 2015 · 9 mos, Hyderabad, India, Worked in defense labs, and helped clients in achieving DO 254 standards using Mentor Graphics EDA tools\. Trained customers on new tools and technologies\. Helped in writing testbench using System Verilog\.

## Education

Bachelor of Technology \(B\.Tech\.\), Electrical, Electronics and Communications Engineering, Chaudhary Charan Singh University , Meerut

[View the original profile](https://tal.club/meet/vimlesh-kumar-2)

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