Vijay Nadpurohit profile photo 1 on Tal

Vijay Nadpurohit

Senior Physical Design Engineer @ Quest-Global

Karnataka

5+ years of work experience

Quest Global
Jan 20251 yr 10 mosPresent

Bengaluru, Karnataka, India

SignOff Semiconductors
Jul 20248 mosFeb 2025

Greater Bengaluru Area

SignOff Semiconductors
Jun 20222 yrs 9 mosFeb 2025

Bangalore

Place • Route • Tapeout • Repeat
OpenFive
Nov 20218 mosJun 2022

Banglore

I performed PnR flow on 2 blocks working on a live project on 6nm technology node Exercising Floorplan activity for better utilisation Analysing timing reports Cleaning DRC's Design Closure
ChipEdge Technologies Pvt Ltd
Oct 20206 mosMar 2021

Banglore

Performed P&R on blocks in Synopsys 28nm technology. Exercise on optimizing floorplan and routing congestion. Increasing design frequency by analyzing and resolving critical timing violations ECO Flow Implementation. Static Timing Analysis and Physical Verification (DRC/LVS). Basic Scripting in BASH, Tcl and Perl. Good Understanding of Physical Design, Static Timing Analysis and Physical Verification. Familiar with Synthesis, Timing constraints, LEC, DRCs and ECO Flow.

Vijay’s AI Stack

claude
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ChatGPT
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Education

Visvesvaraya Technological University

Bachelor of Engineering - BE, Electronics and Communications Engineering

Visvesvaraya Technological University

20173 yrs2020

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Vijay Nadpurohit on Tal

Headline

Senior Physical Design Engineer @ Quest-Global

About

I move blocks for fun😁.

Location

Karnataka

AI stack

claude

gemini

claudecode

ChatGPT

Work experience

Senior Engineer at Quest Global, Jan 2025 - Present · 1 yr 10 mos, Bengaluru, Karnataka, India

Design Engineer 2 Physical Design at SignOff Semiconductors, Jul 2024 - Feb 2025 · 8 mos, Greater Bengaluru Area

Design Engineer 1 Physical Design at SignOff Semiconductors, Jun 2022 - Feb 2025 · 2 yrs 9 mos, Bangalore, Place • Route • Tapeout • Repeat

Engineering Trainee at OpenFive, Nov 2021 - Jun 2022 · 8 mos, Banglore, I performed PnR flow on 2 blocks working on a live project on 6nm technology node Exercising Floorplan activity for better utilisation Analysing timing reports Cleaning DRC's Design Closure

Internship Trainee at ChipEdge Technologies Pvt Ltd, Oct 2020 - Mar 2021 · 6 mos, Banglore, Performed P&R on blocks in Synopsys 28nm technology. Exercise on optimizing floorplan and routing congestion. Increasing design frequency by analyzing and resolving critical timing violations ECO Flow Implementation. Static Timing Analysis and Physical Verification (DRC/LVS). Basic Scripting in BASH, Tcl and Perl. Good Understanding of Physical Design, Static Timing Analysis and Physical Verification. Familiar with Synthesis, Timing constraints, LEC, DRCs and ECO Flow.

Education

Bachelor of Engineering - BE, Electronics and Communications Engineering, Visvesvaraya Technological University

Vijay Nadpurohit - Senior Engineer in Karnataka | Tal