Headline

Senior CPU Cores RTL Design Engineer at AMD || Ex‑Googler || Ex-ISRO || IIT Bombay

About

I am a Hardware Engineering Professional specializing in full-cycle micro-architecture and Superscalar CPU core RTL design. I bring a unique edge to high-performance computing by pioneering AI-enabled SoC integration and LLM-driven automation, recently achieving a 90% reduction in integration planning and IP selection cycles. With a track record of 6 successful tapeouts and a patent in neural-network-based branch prediction, I excel at optimizing complex pipelines and reducing energy-per-instruction to meet aggressive PPA targets. ​I leverage Intelligent Design Systems—utilizing Python and LLMs—to automate IP selection for 130+ instances, while applying deep technical expertise to resolve project-blocking CDC/RDC bugs and complex design bottlenecks. I am driven by the challenge of architecting next-generation, high-issue-width processors and delivering silicon that pushes the boundaries of performance and efficiency.

Location

India

Work experience

CPU Pipeline RTL Design Engineer at AMD, Apr 2026 - Present · 4 mos, Bengaluru, Karnataka, India, -> CPU Pipeline Design. -> Instruction Cache Unit Pipeline Design. -> Branch Prediction Unit Pipeline Design.

Silicon Engineer at Google, Jul 2022 - Apr 2026 · 3 yrs 10 mos, Bengaluru, Karnataka, India, Micro-Architecture & RTL: Led full-cycle design (SystemVerilog) for a complex AXI_BLOCKER IP, solving a critical RDC bug that had halted the project. SoC Integration: Reduced top-level GPU SoC integration time by 75% by implementing AI-driven workflows utilizing LLMs to build integration plans from scratch and manage complex multi-power-domain dependencies. AI-Enabled Design: Engineered a Python-based Intelligent AI system powered by LLMs to automate IP selection for 130+ RAM instances; successfully hit strict PPA constraints while slashing process time by 90%. Verification & Debugging: Resolved ~50 critical CDC bugs and created custom constraints for complex, staggered releases. Timing & Power Closure: Troubleshot and resolved core EDA tool bugs (power integrity, floorplan instability) with CAD/implementation teams. Key Achievements: Contributed to 6 successful tapeouts and filed a patent for a neural-network-based branch predictor.

Education

M.Tech, Integrated Circuit and Systems(ICS), Indian Institute of Technology, Bombay