Headline

Systems Engineer @ Oracle | Building Multi-Agent AI Platforms for Distributed Infrastructure

About

Hey! I'm Vibhor Srivastava. A B.Tech graduate from IIT Dhanbad , I have advanced from a researcher at Transmute AI Lab to a Member of Technical Staff (IC2) at Oracle, gaining deep proficiency in Systems Engineering and Applied AI.My passion lies in bridging the gap between low-level system reliability (C/Linux) and high-level reasoning agents (Generative AI). Building Multi-Agent Orchestrators for Oracle RAC has honed my ability to design scalable, fault-tolerant platforms, while my background in C and Go ensures a strong foundation in concurrency.In my free time, I enjoy reading literature and playing badminton. These pursuits teach me patience and strategy I am always looking for new challenges and opportunities to expand my skillset and knowledge.

Location

Agra

AI stack

claude code

claude

codex

deepseek

gemini

hugging face

Work experience

Member of Technical Staff 2 at Oracle, Sep 2025 - Present · 1 yr, Architecting a Human-in-the-Loop Multi-Agent platform to automate Root Cause Analysis for Oracle RAC. Developing scalable reasoning agents (ReAct) and low-level diagnostic pipelines in C to automatically identify deadlocks and service crashes, reducing manual triage time by 40%.

Member of Technical Staff - I at Oracle, Jun 2024 - Sep 2025 · 1 yr 4 mos, Established a low-level CPU Hang detection pipeline that triggers multi-snapshot stack traces (pstack) to significantly reduce Mean Time to Detect (MTTD). Constructed a memory-efficient generic min-heap API in C for the system monitor daemon, ensuring bounded memory usage for critical kernel slab cache metric collection.

Project Intern at Oracle, May 2023 - Jul 2023 · 3 mos, Remote, enhanced the core OS metric collection framework by implementing Proportional Set Size (PSS) tracking for process-level memory analysis

Research Intern at Transmute AI Lab, May 2022 - Dec 2022 · 8 mos, Conducted research on Knowledge Distillation algorithms for model compression. Successfully achieved a 10x reduction in model size and inference latency on CIFAR-10/100 datasets by experimenting with various teacher-student network topologies.

ML Team Member at Cyber Labs, Jul 2021 - May 2024 · 2 yrs 11 mos, Collaborated on open-source machine learning projects and peer mentorship.

Education

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, Indian Institute of Technology (Indian School of Mines), Dhanbad

Public links

github: https://github.com/sriv2804