Headline

Physical Design Engineer | Trained Fresher | RTL to GDSII | STA | DFT |Synopsys Tools | Trained at Maven Silicon | Passionate about Physical Design | Aspiring VLSI engineer with Verification Expertise

About

I am a passionate and detail-oriented VLSI enthusiast with hands-on training in the end-to-end Physical Design flow (RTL to GDSII). My key areas of focus include: - Floorplanning, Placement, CTS, Routing, and STA - Timing optimization (setup/hold), congestion analysis - Low-power design techniques (UPF), clock domain handling 🧰 Tools: Synopsys ICC2, Fusion Compiler, PrimeTime, Design Compiler 💡 Scripting: TCL, basic Python I’ve also worked on academic and personal projects like: - FIFO-based 1×3 Router - RISCV 🔍 I’m actively looking for opportunities in Physical Design where I can contribute and grow while working on real-world SoC challenges. Let’s connect if you’re hiring or open to discussing VLSI collaboration!

Location

India

AI stack

claude

gemini

grok

notebooklm

openai

perplexity

Work experience

Physical Design Engineer at Maven Silicon, Sep 2025 - Dec 2025 · 4 mos, Hybrid

DFT Engineer at Maven Silicon, Apr 2025 - May 2025 · 2 mos, Bengaluru, Karnataka, India

Physical Design Engineer at Maven Silicon, Aug 2024 - Aug 2025 · 1 y, On-site

Embedded System Using Python at SkillDzire, Jun 2022 - Aug 2022 · 3 mos, Narasaraopeta, Andhra Pradesh, India

Education

Bachelor of Technology - BTech, University College of Engineering Narasaraopet - JNTUK