Headline

PHY & FPGA Engineer | AI/ML for 6G | Senior Project Engineer, 5G Testbed, IIT Kanpur

About

FPGA Engineer experienced in building high-performance digital pipelines on Xilinx UltraScale+ RFSoC platforms. I design and optimize PHY-layer IPs (OFDM, PDCCH, PUCCH) using Vivado HLS and Verilog, with strong focus on timing closure, fixed-point modeling, DSP/BRAM usage, and AXI-based subsystem integration. Hands-on with system-level validation—simulation, wired testing, OTA evaluation, BLER measurements, and deep debug using ILA/ChipScope. Skilled at resolving AXI stalls, FIFO overflows, frame misalignment, and CRC issues across complex HW–SW boundaries. Previously trained in RTL & UVM at Maven Silicon, with experience building reusable IP and verification environments for AXI, AHB, APB, and SPI. I enjoy solving timing-critical design problems, debugging complex systems, and developing clean, production-ready FPGA solutions.

Location

India

AI stack

claude code

Work experience

Senior Project Engineer at Indian Institute of Technology, Kanpur, Apr 2026 - Present · 6 mo, Kanpur

Senior Project Associate at Indian Institute of Technology, Kanpur, Jan 2024 - Mar 2026 · 2 y 2 mo, Kanpur, Uttar Pradesh, India

Project Intern at Maven Silicon, Jun 2023 - Dec 2023 · 7 mos, - Developed expertise in utilizing Synopsys VCS and Design Compiler to facilitate efficient digital design implementation. - Attained proficiency in RTL linting to enforce coding styles, ensuring enhanced readability and reusability. - Actively working on the development of RISC-V design project.

Design Verification Trainee at Maven Silicon, Aug 2022 - May 2023 · 10 mos

Education

Bachelor of Engineering - BE, Electronics and communication engineering, Visvesvaraya Technological University