Headline

FPGA/SoC Design Engineer

About

FPGA Design Engineer specializing in RTL design, verification, microarchitecture, and hardware–software co-design. Experienced in System Verilog/VHDL, SoC integration, embedded firmware, AHB/AXI interfaces, STA, CDC, timing closure, and board-level debugging and validation.

Location

Bengaluru

AI stack

openai

Work experience

Junior Engineer ll at KriSemi Design Technologies, May 2026 - Present · 5 mos, Bengaluru, Karnataka, India, Developing FPGA-based digital systems for satellite-navigation applications. Working on RTL design and integration on the SmartFusion2 platform. Integrating embedded firmware with FPGA logic through AHB-based interfaces and shared memory. Performing simulation, timing analysis, device programming, and on-board debugging using Libero SoC, Synplify Pro, Smart Debug, and Identify. Working on communication interfaces such as MIL-STD-1553B, CAN.

Junior Application Engineer at Unistring Tech Solutions Pvt. Ltd. (UTS), Jul 2024 - Apr 2026 · 1 yr 10 mos, Hyderabad, Telangana, India, Experienced in RTL development and SoC-based FPGA platforms including Zynq Ultra Scale+ ZCU102 and Zynq-7000 devices such as XC7Z020 and XC7Z045. Experienced in developing and integrating custom RTL IPs across Processing System (PS) and Programmable Logic (PL). Worked with Software Defined Radio (SDR) platforms integrating RF transceivers such as AD9361, AD9371, and AD9082, focusing on high-speed data interfacing and FPGA-based implementation. Proficient in the Vivado design flow including synthesis, implementation, timing closure, IP integration, debugging using ILA, and board-level validation

Research Intern at Unistring Tech Solutions Pvt. Ltd. (UTS), Jan 2024 - Jun 2024 · 6 mos, Hyderabad, Telangana, India

Education

BTech, Ece, CVR College of Engineering