Headline

Design Engineer 2 at Cadence || Physical Design Engineer || Static Timing Analysis || physical Verification || Power || EM/IR ||

About

I'm a passionate techie who finds immense joy in crafting chips through hands-on implementation using EDA tools. I have a hands-on expertise in ASIC physical design, adept at managing block-level designs across the entire RTL to GDSII flow. This encompasses synthesis, floorplanning, power planning, CTS, PnR, extraction, STA, logical equivalence, and thorough validation with DRC/LVS and antenna checks. Tool Expertise:- Innovus, Tempus, Genus, Voltus, Pegasus, k2viewer, Conformal, Calibre, ICC2, DC compiler, PrimeTime, Xilinx-vivado.

Location

Bengaluru

AI stack

anthropic apis

claude code

gemini

Work experience

Design Engineer 2 at Cadence, May 2025 - Present · 1 yr 6 mos, Greater Bengaluru Area, Working on implementation of high speed DDR/LPDDRX Design on Lower TechNodes.

Physical Design Engineer at ZOEY SEMICONDUCTORS PVT LTD, Jan 2024 - May 2025 · 1 yr 5 mos, Greater Bengaluru Area, 1) Worked for Texas Instruments on high-speed converters SerDes for automotive SoCs; successfully taped out 3 designs while leading the complete flow from Netlist to GDS, including PNR, STA, power planning, EM-IR analysis, LVS, and DRC 2) Manipulated Clock Tree Synthesis (CTS) using CCOpt by analyzing in trial mode, creating custom skew groups, and fine-tuning clock tree specifications to balance skew and insertion delays 3) Handled functional ECOs with manual clock path tweaking during the ECO stage, resolving double clocking issues, minimum pulse width violations, and setup/hold DRV violations during signoff

Physical Design Engineer at THINSIL, Nov 2022 - Dec 2023 · 1 yr 2 mos, Greater Bengaluru Area, Handled a block-level design from Synthesis to GDSII, covering floorplanning, placement, CTS, routing, timing closure, and physical verification (DRC/LVS)

Physical Design Trainee at RV Skills Design Centre, Apr 2022 - Oct 2022 · 7 mos, Greater Bengaluru Area, • Thorough knowledge of Physical Design concepts ranging from RTL to GDSII. • Acquired extensive knowledge and expertise in ASIC PD Flow involving Floor Planning, Power Planning, IR Drop Analysis, Placement, Clock Tree Synthesis, and Routing. • Acquired knowledge of Linux, TCL, Perl, and Shell Scripting. • Hands-on experience in EDA Tools - Synopsys ICC2 and STA Tools - PrimeTime.

Education

Bachelor of Engineering - BE, Electronic and communication, Gujarat Technological University (GTU)

HSC, Central Board of Secondary Education