Headline

SDE 2 @ Amazon | Ex-Google | Ex-Texas Instruments

About

Software engineer with 7 years split across two halves: 5 years in embedded firmware and silicon validation, then 2 years building AWS backend services and applied GenAI. I build systems end to end: design docs, code, deployment, and on-call. Cloud and AI: at Amazon, backend services and data pipelines on AWS plus AI-powered engineering tools. An LLM-assisted analysis platform on Bedrock and Claude used by 10+ teams and 100+ weekly users; an MCP server exposing live metrics over REST and GraphQL for CLI access; a zero-downtime migration of 400M+ records to Redshift that cut query latency 60%; ingestion at 25K+ updates/day at 99%+ uptime over 12 months. Embedded and silicon: bare-metal C firmware for USB-C PD controllers at Texas Instruments across three chips, covering boot, OTP and register-level work, developed pre-silicon on FPGA and emulators then debugged on first silicon (EVMs, socketed and solder-down boards). At Google, silicon validation and CI for custom silicon platforms: ~2,500 test cases, BootROM debug, boot KPIs, device drivers (I2C, SPI), framework runtime from 6 hours to 2, flakiness ~15% to near-zero. Automated six bench instruments end to end and built an in-house source-level code coverage tool. Most of what I build is infrastructure other engineers depend on, so I care about reliability and about tools people actually adopt.

Location

Greater Bengaluru Area

AI stack

claude

gemini

kiro

obsidian

Cerebras

Work experience

SDE 2 at Amazon, Aug 2026 - Present · 2 mos

SDET II at Amazon, Jul 2024 - Aug 2026 · 2 yrs 2 mos, Working on analytics, developer productivity, and engineering data platforms. - Built and own a Bug Escapes analysis platform (React, PostgreSQL, AWS Lambda, Bedrock + Claude) used by 10+ teams and 100+ weekly active users. Drove ~10% drop in monthly production escapes through best-practice adoption. - Built Playground, a self-serve tool that turns natural-language input into 3-click visualizations and GenAI summaries over Jira and TestRail data, used by managers and leadership for on-demand reporting. - Led a Timestream-to-Redshift migration of 400M+ records over 3 weeks with zero downtime. Cut query latency 60-70% and expanded retention from rolling 6 months to rolling 2 years. - Own a Jira metrics ingestion pipeline on ECS Fargate processing 25K+ issue updates a day across 3 Jira instances, ~200K total Jiras, 99%+ uptime over 12 months. - Built a daily DOSTA metrics pipeline on ECS saving ~8 man-days a month across 4 teams. - Built Shield and ACS executive dashboards on QuickSight (20 role-based views, 2-hour auto-refresh) used weekly by 10+ leaders and 50+ engineers. - Onboarded multiple teams to shared analytics platforms.

Silicon Software Test Engineer at Google, Jul 2022 - Jul 2024 · 2 yrs 1 mo, Worked on silicon validation frameworks and CI infrastructure for Google's gChip platforms, across pre-silicon and post-silicon environments. - Owned ~2,500 test cases across 3 gChip platforms, covering device drivers (I2C, SPI, SLC), access control firmware, and KPI measurement for boot including USB Boot. - Parallelized test execution to cut end-to-end framework runtime from 6 hours to 2 (66% reduction). - Ported the test framework from Java to Python and added cloud-hosted device integration. Brought flakiness on triggered runs from ~15% to near-zero. Took ~2 quarters. - Built a round-robin scheduler for test-case-level scheduling that surfaced ~10% flake rate and drove fixes for one-third of flaky tests via root-cause patterns. - Set up Android presubmit CI from scratch. - Migrated presubmit jobs to new VMs across 8 consumer teams, cutting queue time from 1-6 hours to ~20 minutes. - Drove resolution of virtualization software bugs that were blocking teams from adopting virtualization, unblocking them from emulation wait times. - Built real-time test collector plugins and centralized job dashboards for faster triage. - Mentored 2 new graduate engineers and provided QA oversight for 2 contractors.

Software Engineer at Texas Instruments, Jul 2019 - Jul 2022 · 3 yrs 1 mo, Bangalore Urban, Karnataka, India, USB-C PD firmware validation and embedded test infrastructure across 3 chips: notebook, automotive, and an Apple-partner chip. - Planned firmware validation across Secure/Unsecure Boot, OTP, I2C, SPMI, GPIO, Powerpath, and Register Interfacing in both pre-silicon (FPGA, emulators) and post-silicon (EVMs, socketed and solder-down boards) environments. - Sped up the validation framework from ~5 hours to ~3 hours (~40% reduction) on a pool of ~2,000 tests, used by 4 engineers daily. - Automated 6 bench instruments: Saleae Logic Analyzer, Keil Debugger, Acroname USB-C Switch, Prodigy SPMI Exerciser, Totalphase PD Analyzer, Teledyne LeCroy USB-C PD Analyzer. Saved ~30 min/day per engineer and enabled single-go full test runs. - Built a pre-silicon to post-silicon abstraction layer to minimize test-code changes across environments. Partnered with digital design engineers across multiple RTL revisions. - Built an in-house source-level code coverage tool with path-to-test mapping and visual reports, which exposed untested code paths and drove targeted test expansion. - Built a Tkinter-based internal GUI debugger that broadened tool adoption beyond the core CLI users, including engineers from sister teams. - Built a custom I2C analyzer plugin for Saleae used by ~15 engineers. - Authored a peer-reviewed paper at TI India Technical Conference 2022 on automated test-case generation. Accepted at ~10% rate, presented to 500+ engineers. Surfaced 40 new test cases in a pool of 250 and cut manual test planning from 5 days to 1 day per engineer. - Awards: Global Recognition Gold (Mar 2022), Silver x2, Automation Champion (Dec 2021), Budding Talent (Dec 2020). - Mentored 2 new graduate engineers during chip bring-up and validation.

President at IMAGES_CHANDIGARH, Dec 2018 - May 2019 · 6 mos, Chandigarh, India

Software Engineer Intern at Texas Instruments, Jan 2018 - Jul 2018 · 7 mos, Bengaluru, Karnataka, India, USB-C PD embedded controller framework, in C on a Tiva microcontroller. - Built an Embedded Controller framework from scratch in C, interfacing with the USB-C PD Controller over I2C and ADC. - Improved customer scenario replication coverage from 35% to 75% by adding illustrative examples and strategic plug points, including patch download and multi-interrupt cases. - Framework was in active team use through my subsequent full-time tenure at TI from 2019 to 2022.

Member at IMAGES_CHANDIGARH, Feb 2016 - May 2019 · 3 yrs 4 mos, Chandigarh, India

Education

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, Punjab Engineering College