Headline

Design Verification Engineer @ metavlsi || CPU Cores team @ AMD

About

Specialized in exhaustive hardware verification using mathematical proofs and Assertion-Based Verification (ABV). Expert in identifying deep-cycle corner cases within high-performance CPU pipelines and complex arithmetic DataPaths. Proficient in Synopsys VC Formal and SystemVerilog Assertions (SVA), focusing on ensuring architectural integrity for Zen 7 architecture. Core Impact: Accuracy: Consistently achieved 100% proof convergence on DPV of execution stage logic. Efficiency: Reduced verification cycle time by 60% by transitioning simulation-heavy blocks to Formal Property Checking. Bug Detection: Uncovered 3 critical logic bugs that escaped traditional OVL simulation-based flows. Technical Stack: Synopsys VC Formal, SystemVerilog Assertions (SVA), JasperGold, TCL, and Shell Scripting. Currently employed at metavlsi as Formal Verification Engineer.

Location

India

AI stack

claude code

codex

Work experience

Design Verification Engineer at metavlsi, Aug 2025 - Present · 1 y 1 mo, Bengaluru, Karnataka, India, Client: AMD India Private Ltd Team: CPU Cores - FV team Responsibilities: - Worked on writing assumes for interface signals and resolved 5+ OVLs for Zen 7 project. - Owned the Datapath verification of 10+ types of opcodes, achieveing 100% pass rate for Zen 8. - Wrote TCL and Shell scripts to automate our internal flows, cutting down manual setup time by about 50%.

Intern at AMD, Aug 2024 - May 2025 · 10 mos, Bengaluru, Karnataka, India, - Applied formal methods to the x86 CPU pipeline, specifically targeting complex DataPath and arithmetic blocks. - Instead of just "writing code," I spent time analyzing the architectural state space to write SVAs that caught 3 corner-case bugs that simulation missed. - Used Synopsys VC Formal to drive blocks to full convergence, proving that the hardware would behave correctly under every possible legal input. - Collaborated with senior engineers to refine design constraints, ensuring the formal environment accurately modeled the execution stage of Zen7

Embedded Software Engineer at HCLTech, Jan 2023 - Aug 2023 · 8 mos, Chennai, - Done debugging on embedded C++ and handled 5+ Jira tickets - Presented some changes need to be implemented in code, to clients - Titled as Senior Software Engineer under HCLTech

Software Engineer at HCLTech, Oct 2021 - Dec 2022 · 1 yr 3 mos, Chennai

Trainee at HCLTech, Aug 2021 - Sep 2021 · 2 mos, Remote, Get trained on C, C++, OOP, and embedded C++

Education

Master of Technology - MTech, VLSI Design, Vellore Institute of Technology

Bachelor of Technology - BTech, Electrical and Electronics Engineering, Vellore Institute of Technology