Headline

Engineering Leader @ Altera | RTL design, verification, post-si validation and ATE

About

Accomplished semiconductor executive with 27 years of progressive leadership across SoC architecture, IP integration, and large-scale engineering management. Proven track record of defining and delivering multi-generation IP/ SoC roadmaps spanning advanced process nodes for industry-leading microprocessors, server SoCs, and FPGA platforms. Skilled at translating market and product requirements into silicon strategies, driving cross-functional alignment across global organizations, and building high-performing engineering teams of 40+. Expert in full-chip development lifecycle — from architecture and RTL through silicon bring-up, validation, and productization — with deep expertise in high-speed serial IOs, memory subsystems, and SoC integration.

Location

Bengaluru

AI stack

claude

Work experience

Senior Engineering Manager at Altera, Jan 2025 - Present · 1 yr 9 mos, Bengaluru, Karnataka, India, Altera has officially transitioned into a standalone company as of January 2025, assuming responsibility for the former Intel Programmable Solutions Group (PSG) products.

Senior Engineering Manager at Intel Corporation, Nov 2021 - Dec 2024 · 3 yrs 2 mos, Bengaluru, Karnataka, India, Leading & managing multiple FPGA IP RTL design & verification teams of ~40 engineers delivering class-leading FPGA IPs like Ethernet, PCIe SS, HSSI SS & QHIP for current & next-generation Intel® FPGA portfolio (Intel® Agilex™, Intel® Stratix® 10, etc.) Driving multiple FPGA IP development as a program sponsor for current & next-generation Intel® IPUs & ADPs. Actively driving the process of hiring, coaching, mentoring, appraisals, retention, employee’s career growth & organization’s growth to build strong & sustainable engineering teams for larger teams within & beyond my direct organization.

Engineering Manager at Intel Corporation, Apr 2020 - Nov 2021 · 1 yr 8 mos, Bengaluru, Karnataka, India, Spearheaded multiple RTL design & verification teams driving the development of multiple IPs like LPSS, ICE, THC, FMHC, SCS IPs on Intel (7nm & 10nm), TSMC (N6) & Samsung (S14) foundry that works as a building block for multiple SoCs in diverse segments from desktop processors to discrete graphics to Xeon server processors. As IP Execution Manager, built efficient teams by introducing & enabling new techniques for tracking & quality of IPs to a 100% PAS rate for all the IPs owned. Drove many people-specific strategic initiatives toward making the org a Great Place To Work.

Soc Design Eng Manager at Intel Corporation, Jun 2014 - Apr 2020 · 5 yrs 11 mos, Bengaluru, Karnataka, India, Led multiple RTL design & verification teams responsible for: 1) Driving the development of multiple IPs such as HBMIO2e, MDIO (Die-to-Die), PCIe Gen3, MC+DDRIO & GPIO subsystem on Intel (7nm & 10nm) foundry that was productized on multiple Xeon class server SoCs. 2) Driving the development of next-generation 7nm memory/ DDRIO Test Chip SoC. This was a brand new organization that was built from "zero" which quickly went from forming, storming, norming to performing; to deliver the 7nm memory/ DDRIO Test Chip SoC in the shortest time of fewer than 2 quarters. In addition to RTL design & Verification, led the physical design team owning a 10nm MC+DDRIO subsystem to drive end-to-end design PLC from front end to back end (structural design). Spearheaded Agile/ Scrum implementation within server IP front-end teams in India to achieve greater efficiencies. Worked as hands-on SoC Design Engineer on 10nm DDR4 & DDR5 IO functional verification, analog mixed-signal (AMS/ MSV) verification & led DFx verification.

Test Specialist at APC by Schneider Electric, Mar 2004 - Nov 2004 · 9 mos, Bengaluru, Karnataka, India, Key person in implementing a new test & burn-in setup for testing the very first designed in India inverter for APC. Identified & implemented a process to reduce the rate of failure of APC UPS due to USB errors during final testing on ATEs which helped to reduce the rate of false failures & hence improving the overall manufacturing yield.

Test Engineer at Jabil (Celetronix), Jan 2001 - Mar 2004 · 3 yrs 3 mos, Mumbai, Maharashtra, India, Successfully defined the test plan using memory test algorithms for SDRAM & DDR memories. Successfully defined the methodologies for efficient fault analysis & yield improvement in ATE (Advantest, Teradyne, Fairchild Xincom, etc.) environment. Completed design validation & production test for SDRAM & DDR for Micron. Achieved technology transfer & qualification of various products like memory (SDRAM/ DDR modules), motherboards, satellite receivers, RFID & audio amplifiers & enabled the products for volume manufacturing. Successfully installed & qualified 12 Teradyne J994 & 2 Advantest T-5371 testers in Jabil Mumbai.

Tr. Test Engineer at APAR Industries Limited, Jun 1999 - Dec 2000 · 1 yr 7 mos, Valsad, Gujarat, India, Verified the raw optical fiber & optical fiber cables for various optical & mechanical parameters viz. attenuation, length, spectral attenuation, chromatic dispersion, coating, color curing, cladding diameters, stress, water slippage, etc. Ensured the quality of the finished cables as well as all process products by maintaining high standards at the production line itself for various parameters according to the company’s standards.

Education

MS, VLSI Design, Manipal Academy of Higher Education

Bachelor of Engineering, Electronics Engineering, Savitribai Phule Pune University