Headline

VLSI & Physical Design Engineer | FPGA · Versal · Zynq · HLS IP | M.Tech VLSI | Semiconductor Enthusiast

About

Passionate VLSI & Physical Design Engineer currently working at AMD, one of the world's leading semiconductor companies. I specialize in FPGA-based system design, HLS IP development, and hardware bring-up using AMD/Xilinx Versal and Zynq platforms. With a strong foundation from my M.Tech in VLSI (9.2 GPA) and hands-on expertise in Cadence Virtuoso, Xilinx Vivado, and Vitis, I bring both academic depth and real-world industry experience to every project I work on. My core strengths include: 🔧 RTL design, synthesis, and layout for digital/analog circuits 📡 HDMI pipeline workflows and system-level debugging 💡 HLS IP development and design customization on Versal/Zynq 🛠️ Hardware validation and bring-up for multimedia SoC solutions I thrive at the intersection of hardware and software, and I'm passionate about pushing the limits of chip design as semiconductors power the next wave of AI, edge computing, and high-performance computing. Always learning. Always building. Open to collaborations, technical discussions, and exciting opportunities in VLSI, SoC, and chip design. 📩 hasrithatikkireddy@gmail.com

Location

Amalāpuram

AI stack

claude code

cursor

Work experience

VLSI Engineer at AMD, Dec 2025 - Present · 10 mos, Hyderabad, Working on FPGA-based multimedia solutions using AMD/Xilinx Versal and Zynq platforms. Involved in HLS IP development, design customization, validation, hardware bring-up, HDMI pipeline workflows, and system-level debugging using Vitis and Vivado tools.

Application Specific Integrated Circuit Engineer at TECHNICAL HUB, Jun 2024 - Dec 2024 · 7 mos, 1. Designed and implemented RTL logic and layout for digital circuits using industry-standard EDA tools. 2. Performed logic synthesis and timing analysis using Cadence and Xilinx Vivado toolchains. 3. Gained hands-on experience in DSCH-based schematic design and responsive circuit optimization. 4. Contributed to chip design flows from specification to post-layout verification.

Education

VLSI Design, Aditya University

Electronics and Communication, BVC ENGINEERING COLLEGE - ODALAREVU (BVCE)