---
title: "Tarun Kumar Majji - ASIC Design Verification Engineer in Razam | Tal"
description: "Meet Tarun Kumar Majji, ASIC Design Verification Engineer | NoC | SoC Verification | PCIe | UCIe | AMBA | System Verilog/UVM based in Razam."
image: "https://tal.club/meet/tarun-kumar-majji/share-image"
---

# Tarun Kumar Majji on Tal

## Headline

ASIC Design Verification Engineer \| NoC \| SoC Verification \| PCIe \| UCIe \| AMBA \| System Verilog/UVM

## About

Design Verification Engineer \| PCIe \| UCIe \| AMBA \| NoC \| SoC Verification \| SystemVerilog \| UVM \| C I build verification environments that catch bugs before silicon does\. With 2\+ years of hands\-on experience in IP, VIP, and SoC\-level verification, I specialize in constructing UVM testbenches from scratch and driving designs to 100% functional coverage closure the kind of work that directly impacts tapeout quality\. My day\-to\-day revolves around: o Verifying complex protocols like PCIe Gen3/Gen5, UCIe 1\.1, AXI, AHB, APB, and SPI o Building scalable UVM environments for IP and subsystem\-level verification o Writing SystemVerilog Assertions \(SVA\) and functional coverage models o C\-based verification for CPU subsystems and SoC\-level validation o Debugging with Synopsys VCS & Verdi waveform analysis, root\-cause isolation, and coverage\-driven closure What sets me apart is not just knowing the tools it's understanding why a test fails and how to fix it efficiently\. I've worked on real\-world projects including PCIe Gen5 VIP, UCIe 1\.1 VIP, SSD Controller SoC, AHB\-to\-APB Bridge, SPI IP, Router Design & Verification, and Dual\-Port RAM SoC Verification giving me solid exposure to both block\-level and system\-level thinking\. I thrive in collaborative environments, communicate clearly across teams, and I'm always pushing to go deeper whether that's mastering a new protocol, optimizing coverage, or debugging a tricky corner case at 2am\. Currently open to opportunities in Design Verification Engineer\. 📩 Let's connect if you're working on next\-gen silicon\.

## Location

Razam

## Work experience

ASIC Design Verification Engineer at Scaledge Technology, Jun 2024 \- Present · 2 yrs 4 mos, Bengaluru, Karnataka, India

Advanced Design and Verification Trainee at Maven Silicon, Aug 2023 \- Jun 2024 · 11 mos, Bengaluru, Karnataka, India

## Education

Bachelor of Technology \- BTech, Electronics and Communication Engineering, aditya institute of technology and management

[View the original profile](https://tal.club/meet/tarun-kumar-majji)

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