Headline

Machine Learning and Software Engineer with 15+ years of experience in EDA tool development. Expertise in timing optimization, ASIC flow automation, and PCB design. Passionate about leveraging AI to enhance chip design

About

Ph.D. graduate in Computer Engineering from the University of Utah with quality experience in Electronics Design and Automation industry as an Application Engineer. Specialties: * Machine learning in EDA * Relative Timed Design Flow Expert - Synopsys Design Compiler, PrimeTime, IC-Compiler, Modelsim. * Expert in the usage of application extension languages and experienced in providing solutions using them - TCL, SKILL, C++, python. * Understanding of Library Design and ASIC Flow - Virtuoso, NCSIM, RTL Compiler; VERILOG. * Expertise in PCB Design Flow and Cadence PCB Tools - Allegro PCB Editor, Allegro Package Designer, Constraint Manager, Specctra, SigXP, PCB Librarian, Allegro Design Entry HDL, OrCAD - Allegro Design Entry CIS, PSPICE 10.5, OrCAD Layout * Understanding of Virtuoso to PCB Flow - to concurrently design chip, package, and PCB.

Location

Fremont

Work experience

Principal Design Engineer at Multigig startup, Jun 2025 - Present · 1 yr 1 mo, San Jose, California, United States

Sr Principal Solutions Engineer at Cadence Design Systems, Jul 2023 - Feb 2025 · 1 yr 8 mos

Sr. R&D Engineer at Synopsys Inc, Jan 2020 - Jul 2023 · 3 yrs 7 mos, Hillsboro, Oregon, Software development in python, ML, tcl, C/C++. Adding svf support for DW in FC and DC.

Sr. Design Engineer at Marvell Semiconductor, Oct 2019 - Dec 2019 · 3 mos, Boise, Idaho Area

Graduate Research and Teaching Assistant at University of Utah, Jan 2014 - Sep 2019 · 5 yrs 9 mos, Salt Lake City

Education

Doctor of Philosophy (PhD), Electrical and Computer Engineering, University of Utah

M.Sc, Electronics, University of delhi