Headline

ASIC design engineer

About

An accomplished M.Tech graduate in Microelectronics and VLSI from IIT Hyderabad with a CGPA of 8.6. Experienced Lead RTL Design Engineer at GPMU Semiconductors with expertise in ASIC RTL design, synthesis, lint, CDC, functional verification with AMS simulations. Proficient in Verilog, System Verilog, and various EDA tools. Demonstrated leadership skills in training teams and presenting at tech exhibitions. My expertise extends to I3C, I2C, SPI, CRC, packet decoder, fault detection logic, IC interfaces complemented by strong conceptual knowledge of STA, timing closure, and protocols such as AMBA APB. Author of publication "Fabrication of Si Membrane using Frontend Bulk Micromachining".

Location

Hyderabad

AI stack

gemini

openai

perplexity

Work experience

Senior ASIC RTL designer at Quest Global, Feb 2026 - Present · 6 mos, Hyderabad, Telangana, India

ASIC Design Engineer at Green PMU Semi Pvt Ltd, Oct 2024 - Present · 1 yr 10 mos, Hyderabad, Telangana, India, SGIL LED driver : The ASIC design includes digital interface, packet decoder, OTP memory, frame buffers, PWM in its datapath. It is supported by a robust control path capable of performing fault detection, CRC and parameter adjustments. • Developed the top module to support multiple operational modes, including test patterns, CRC, and fault detection, achieving a 22% area improvement by optimizing counter blocks. • Integrated Packet decoder for diverse data types. Implemented a robust control path FSM for multiple communication protocols (i2c, i3c, SPI, GPIO). • Designed control path for data handling and diagnostics, along with adaptive power management and fault detection features for enhanced reliability. • Optimized PWM control and cross-hatch test patterns for efficient LED matrix management.

ASIC Design Engineer at Green PMU Semi Pvt Ltd, Feb 2023 - Sep 2024 · 1 yr 8 mos, Hyderabad, Telangana, India, SparkGF-2 SparkGF-2 is a cutting edge ultra-low power energy harvesting IC. The ASIC included i2c protocol, gpio interface, OTP trimming blocks. Digital logic was exclusively designed to meet the ultra-low power requirements by the PMIC. • Developed and optimized digital interfaces supporting I2C and GPIO protocols, including I2C envelope and packet decoder design. Collaborated with the DV team to create and execute debug test cases. • Designed and implemented RTL code for the OTP trimming block, ensuring functional accuracy and adherence to specifications. Optimized the design based on timing, area and power reports. • Modelled schematic testbenches using netlists and conducted AMS simulations for functional validation. SparkGF-1 Contribute in development of RTL code for OTP trimming block Designed and developed RTL codes for small IPs using Verilog in Questasim Developed test cases to debug designs with DV team Performed lint checks for designed IPs. Analyzed timing reports, Gate count of the IP Modified RTL files for import into Virtuoso for AMS simulations

ASIC Design Engineer at Green PMU Semi Pvt Ltd, Aug 2022 - Jan 2023 · 6 mos, Hyderabad, Telangana, India, SparkTSMC-1 Experience in developing verilog model for I2C slave block Defined and designed behavioral models for analog blocks for functional verification Responsible for designing TCL scripts for synthesis constrains Converting netlists into AMS simulations on cadence Virtuso for signal verifications Modelled schematic testbenches using netlist and performed AMS simulations

ASIC Design Engineer at Internshala, Aug 2024 - Sep 2024 · 2 mos, India, Internship (From Internshala online courses): VLSI design with case studies The training mainly focused on RTL design aptitude development. It included study of RTL design flow, pipeline architecture, AMBA architecture . • Implemented a 2-way set-associative cache with LRU replacement and write-back support • Devised and executed 16-bit ALU with a pipelined architecture optimizing the area for data and control path FSM • Acquired expertise in VLSI design methodologies, emphasizing best practices and leveraging artificial intelligence (AI) for RTL design flow optimization.

Education

Master of Technology - MTech, VLSI and Microelectronics, Indian institute of technology Hyderabad

Bachelor of Technology (B.Tech.), Electronics Engineering, walchand college of engineering