---
title: "Suyash Agrawal - Design Engineer in Hyderabad | Tal"
description: "Meet Suyash Agrawal, FPGA Design Engineer based in Hyderabad. AI stack includes claude code, claude, and gemini."
image: "https://tal.club/meet/suyash-agrawal-1/share-image"
---

# Suyash Agrawal on Tal

## Headline

FPGA Design Engineer

## Location

Hyderabad

## AI stack

claude code

claude

gemini

geminicli

ChatGPT

Microsoft Copilot

## Work experience

Design Engineer at Microchip Technology Inc\., Jul 2024 \- Present · 2 yrs 5 mos, \- Developed and modified test environments for RTL\-based hardware IP\. \- Analyzed protocol specs and design behavior for functional validation\. \- Created timing\-aware testbenches targeting critical design signals\. \- Applied verification strategies to improve coverage and identify corner cases\.

Intern at Microchip Technology Inc\., Jan 2024 \- Jun 2024 · 6 mos

Teaching Assistant at BITS Pilani, Hyderabad Campus, Sep 2022 \- Jan 2024 · 1 yr 5 mos, Hyderabad, Telangana, India, Responsibilities included grading papers, administering quizzes, managing mark uploads, supervising labs, and providing support to the course instructor\.

Assistant System Engineer at Tata Consultancy Services, Apr 2021 \- Apr 2022 · 1 yr 1 mo, Kolkata, West Bengal, India, Worked in the domain of Cloud Infrastructure Management, VMWare Technologies and Troubleshooting\.

## Education

Master of Engineering \- ME, Embedded Systems and VLSI Design, BITS Pilani, Hyderabad Campus

Bachelor's degree, Electrical and Electronics Engineering, Institute of Engineering & Management \(IEM\)

[View the original profile](https://tal.club/meet/suyash-agrawal-1)

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