Suyash Agrawal
FPGA Design Engineer
Hyderabad
5+ years of work experience
Jul 20242 yrs 5 mosPresent
- Developed and modified test environments for RTL-based hardware IP.
- Analyzed protocol specs and design behavior for functional validation.
- Created timing-aware testbenches targeting critical design signals.
- Applied verification strategies to improve coverage and identify corner cases.
Jan 20246 mosJun 2024
Sep 20221 yr 5 mosJan 2024
Hyderabad, Telangana, India
Responsibilities included grading papers, administering quizzes, managing mark uploads, supervising labs, and providing support to the course instructor.
Apr 20211 yr 1 moApr 2022
Kolkata, West Bengal, India
Worked in the domain of Cloud Infrastructure Management, VMWare Technologies and Troubleshooting.
Suyash’s AI Stack
Education
Master of Engineering - ME, Embedded Systems and VLSI Design
BITS Pilani, Hyderabad Campus
20222 yrs2024
Bachelor's degree, Electrical and Electronics Engineering
Institute of Engineering & Management (IEM)
20164 yrs2020
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