---
title: "Suryamoy Mondal - Senior Design Verification Engineer in Bengaluru | Tal"
description: "Meet Suryamoy Mondal, Working as DV Engineer Having Knowledge in Verilog, System Verilog, UVM, Protocol Pcie,DDR4 , SPI, AXI , Qualified GATE exam (ECE, IN) based in Bengaluru. AI stack includes claude."
image: "https://tal.club/meet/suryamoy-mondal/share-image"
---

# Suryamoy Mondal on Tal

## Headline

Working as DV Engineer Having Knowledge in Verilog, System Verilog, UVM, Protocol Pcie,DDR4 , SPI, AXI , Qualified GATE exam \(ECE, IN\)

## About

https://topmate\.io/suryamoy\_mondal

## Location

Bengaluru

## AI stack

claude

## Work experience

Senior Design Verification Engineer at AMD, Apr 2025 \- Present · 1 yr 6 mos, Bengaluru, Karnataka, India, AMD client through Quest Global

Design Verification Engineer at Qualcomm, Nov 2023 \- Nov 2024 · 1 yr 1 mo, Bengaluru, Karnataka, India, QUALCOMM client through Smartsoc

Design Verification Engineer at RAITON SEMICONDUCTOR PVT LTD, Mar 2022 \- Oct 2023 · 1 yr 8 mos

Doctoral Student at Indian Institute of Technology \(Indian School of Mines\), Dhanbad, Aug 2020 \- Aug 2021 · 1 yr 1 mo

Junior Researcher at Department of Science and technology, Oct 2019 \- Aug 2020 · 11 mos

## Education

Master of Technology, Microelectronics and VLSI, Maulana Abul Kalam Azad University of Technology, West Bengal \(MAKAUT, WB\)

Doctor of Philosophy \- PhD, VLSI, Indian Institute of Technology \(Indian School of Mines\), Dhanbad

[View the original profile](https://tal.club/meet/suryamoy-mondal)

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