Headline

Design Verification Engineer at NXP Semiconductors

About

Most designers fall in love with how their architecture should behave. My job is to be the resident skeptic who figures out how to ruin its day. I work in semiconductor verification, building environments that push mixed signal designs past their comfort zones. It’s an adversarial craft, but it’s also fundamentally collaborative: every edge-case bug caught in pre-silicon simulation is a disaster that never makes it to the lab bench. With a background in Electronics and Instrumentation and practical work in robotics, I developed an obsession for systems-level mechanics and an absolute low tolerance for manual friction. When I build a verification flow, I focus on two things: Stress the corners: Randomizing stimulus until the unwritten spec assumptions fall apart. Build real leverage: Writing the automation, harness tooling, and scripts that turn fragile regression cycles into clean, deterministic pipelines. It’s easy to write a testbench that passes. Building one that systematically finds the needle in the silicon haystack is where the engineering actually begins. Always down to trade notes with folks working on complex digital hardware, verification architecture, and automated developer tooling for silicon.

Location

Pune Division

AI stack

anthropic apis

claude code

claude

gemini

github copilot

hugging face

Work experience

Lead Design Verification Engineer at NXP Semiconductors, Oct 2026 - Present · 2 mos

Senior Design Verification Engineer at NXP Semiconductors, Apr 2024 - Sep 2026 · 2 yrs 6 mos, Bengaluru, 1) Engineered scalable AI verification systems by developing custom MCP servers, autonomous agents, and structured workflows, integrating them directly into internal tools to enhance verification precision. 2) Verified mixed‑signal automotive ICs for LED controllers and battery management systems, ensuring robust functionality and safety compliance. 3) Developed and debugged verification environments using CAN, SPI, I2C , JTAG and UART protocols for reliable on‑chip communication and test modes. 4) Executed formal property and connectivity verification using Cadence JasperGold (FPV, Connectivity), authoring SVA properties and constraints. 5) Built Python and AI‑based automation to accelerate regressions, log analysis and coverage reporting, boosting verification productivity by 2-3x. 6) Led coverage planning and closure for critical IP blocks, owning verification for 5 successful tapeouts from bring‑up to sign‑off. 7) Presented the paper Regression Run Time Optimization using Verisium Smart Run in Cadence Connect

Design Verification Engineer at NXP Semiconductors, Jul 2023 - Apr 2024 · 10 mos, Bengaluru, Karnataka, India

Software Engineering Intern(AI/ML) at Texas Instruments, Jan 2023 - Jun 2023 · 6 mos, Bengaluru, Karnataka, India, Low Power Audio 1) Developed an automatic audio EQ solution which would help in reducing time to market for new products and reduce manual errors. 2) The automatic audio EQ generates a filter system which gives the desired frequency response based on raw inputs and desired outputs. 3)Automatic Dynamic EQ system also implemented which performs equalization based on signal level of audio. 4) Developed a Voice activity detection system which is able to achieve significant accuracy in low SNR environments. 5)The voice activity detection system has low power and memory requirements, suitable to be deployed on edge devices.

AI Intern at TML Business Services Limited, May 2022 - Jul 2022 · 3 mos, Pune/Pimpri-Chinchwad Area, 1)Developed a Vision system to detect key features from vehicle tyres for warranty claim purposes. 2) Utilised various low power technologies such as Raspberry Pi and Jetson Nano for deploying models onsite at industrial locations. 3)Utilised object detection for selecting areas of relevant text from images and video feed. 4)Perform Optical Character Recognition to read text and then generate QR code containing information about the tyre. 5)Bundled all the functionalities as a GUI application.

Summer Intern at CSIR - National Institute of Oceanography, May 2021 - Jul 2021 · 3 mos, Goa, India

Education

Master of Technology, Artificial Intelligence, Indian Institute of Technology, Madras

Bachelor of Engineering - BE, Electronics and Instrumentation, Minor in Robotics and Automation, BITS Pilani, Hyderabad Campus

Public links

github: https://github.com/SupratimChatterjee5

medium: https://medium.com/@suparanrocks

supratimportfolio.vercel.app: https://supratimportfolio.vercel.app/