---
title: "Sunil Pandey - Senior Lead Design and Verification Engineer in Greater Bengaluru Area | Tal"
description: "Meet Sunil Pandey, Senior lead Design and Verification Engineer @ Safran | DO-254, RTL Design and Verification, VHDL, SV, UVM in Aerospace, HFT in FinTech based in Greater Bengaluru Area. AI stack includes claude code, claude, and codex."
image: "https://tal.club/meet/sunil-pandey/share-image"
---

# Sunil Pandey on Tal

## Headline

Senior lead Design and Verification Engineer @ Safran \| DO\-254, RTL Design and Verification, VHDL, SV, UVM in Aerospace, HFT in FinTech

## About

As a Senior lead Design and Verification Engineer at Safran, I contribute to developing and executing verification strategies aligned with DO\-254 standards\. My role includes creating test plans and benches using SystemVerilog and UVM, reviewing RTL designs, and generating verification artifacts such as trace matrices and coverage reports\. I also support hardware testing on FPGA platforms to ensure high\-quality deliverables\. Experience in RTL design and verification, significantly impacting aerospace and defence projects\. Proven ability to lead teams effectively, ensuring seamless execution of complex projects while maintaining rigorous documentation standards\. Strong proficiency in debugging, simulation and hardware on FPGA platforms, utilizing advanced tools and methodologies to achieve optimal outcomes\. Experience in Development of HFT low latency trading environment platform and algorithm strategy\.

## Location

Greater Bengaluru Area

## AI stack

claude code

claude

codex

deepseek

gemini

notebooklm

## Work experience

Senior Lead Design and Verification Engineer at Safran, Jul 2025 \- Present · 1 yr 4 mos, Bengaluru, Karnataka, India

Senior Lead Design and Verification Engineer at Collins Aerospace, Apr 2023 \- Jul 2025 · 2 yrs 4 mos, Bengaluru, Karnataka, India

Senior Design and verification Engineer at Collins Aerospace, Nov 2019 \- Jul 2021 · 1 yr 9 mos, India

Senior Design and Verification Engineer at Altran, Oct 2018 \- Nov 2019 · 1 yr 2 mos, Bangalore

Senior Hardware Design Engineer at Quantizer Research, Mar 2017 \- Sep 2018 · 1 yr 7 mos, South Delhi, Delhi, India

## Education

Bachelor of Engineering \(BE\), Electronics and Communications Engineering, college of technology and engineering udaipur\.

12th, Mathematics, physics, chemistry, Maa bharati senior secondary school, kota

[View the original profile](https://tal.club/meet/sunil-pandey)

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