Headline

LPDDR6 Memory Controller IP DV Lead

About

13 years of IP/Subsystem Design Verification experience in VLSI industry . I have worked in various domains of SoC like System Cache, Interconnects, Memory Controller, PMIC etc. Currently working as part of Memory Controller IP DV at Google, leading IP DV efforts for one of the cutting edge DRAM controller. Previously, I was involved in System Cache Controller IP level design verification at Qualcomm BDC. At Qualcomm, I was leading IP DV efforts across several projects along with working on setting up new methodologies like Formal Verification and Simulation Acceleration (Veloce) within the team. Skills : - Functional Verification - Simulation Acceleration using Veloce - Formal Verification - UVM, SV , C/C++ - Perl and Python based scriptin

Location

Greater Bengaluru Area

AI stack

antigravity

gemini

hugging face

ollama

openai

windsurf

Work experience

Sr Silicon DV Engineer at Google, Aug 2023 - Present · 3 yrs 1 mo, Bengaluru, Karnataka, India, Leading Design Verification of Memory Controller IP based on next gen LPDDR technology

Staff Engineer - Design Verification at Qualcomm, Nov 2021 - Aug 2023 · 1 yr 10 mos, Bangalore Urban, Karnataka, India, -Worked as a part of Last Level Cache Controller IP DV team. -Involved in leading IP Verification efforts across several projects for LLCC at Qualcomm. -Occasionally co-ordinate with Subsystem and SoC DV teams to identify DV requirements and provide IP data accordingly -Bringing up UVM and DPI based veloce testbench for new projects -Setting up new methodologies like Formal and Veloce Skills - UVM, Veloce, emulation, simulation, perl scripting, debugging, formal

Senior Lead Engineer at Qualcomm, Jun 2019 - Nov 2021 · 2 yrs 6 mos, Bengaluru

Computer Vision Engineer at Intel Corporation, Nov 2018 - Jun 2019 · 8 mos, Bangalore, Artificial Intelligence Products Group (AIPG) Currently working on Design Verification of Tensor Processor SubSystem in Neural Network SoC at intel.

Senior SoC Verification Engineer at Intel Corporation, Jun 2016 - Nov 2018 · 2 yrs 6 mos, Bangalore, High Performance Group (HPG) Worked on functional verification of next generation IoT/Client Intel SoCs. Main focus areas are validation of LPDDR4 ,DDR4 based memory subsytems , Intel Proprietry SoC interconnects and their power management. Worked on the initial SoC validation health bringup and developed repo check-in gating tests to maintian SoC health, gained knowledge of the SoC bringup flow Was also involved in Co-Validation of PMIC and Current Voltage Regulator(IVR) based SoC designed for next generation mobile/client systems. Skills developed : OVM/UVM with SV based verification, Verification approach planning, Complete ownership of unit testbench and shared ownership of SoC testbench , Testplan development and coverage closure, Testcase development, responsible for seamless porting of owned unit TB components to SoC testbench, perl and shell based scripting, git and svn Protocols : DDR4, LPDDR4, LPDDR5, AXI, APB, Intel proprietry protocols

Verification Engineer at Arm, Aug 2014 - Jun 2016 · 1 yr 11 mos, Bengaluru, Karnataka, India, Working in Systems and Software group at ARM in elements verification team. Responsibilties included : - Ownership of several sub-modules and Testbench/Test environment development using SV and UVM - C/C++ based top level testcase development along with TB components ownership - Functional, Toggle and Code coverage closure of modules owned - Verification infrastructure development and maintainence using Perl,Shell,PHP etc. - debugging failures using questasim

System Architect at NVIDIA, Jul 2013 - May 2014 · 11 mos, Bengaluru, Karnataka, India, Tegra Performance Verification - Developed C++ based perf test for various Tegra subsystem modules. - Managed the perf-verif infrastructure including perl,python and shell scripts - Managed the perf-monitors plugged into RTL for post-processing and data-analysis

Intern at NVIDIA, Jan 2013 - Jun 2013 · 6 mos

Education

B.E.(Hons), Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani

Mathematics and Computer Science, Delhi Public School, Bhilai