Headline

Staff Engineer(PD/STA) @Samsung | Ex -Intel | VIT-Vellore

About

As a SoC Design Engineer , my focus is on Static Timing Analysis for server SoCs, ensuring impeccable timing closure and signoff. The technical landscape I navigate includes advanced 10nm and 7nm technology nodes, where my contributions have been pivotal in the convergence of critical partitions. My expertise with EDA tools like IC Compiler II has been instrumental in achieving our team's goals. With a Master's degree in VLSI Design from Vellore Institute of Technology, I bring a robust educational foundation to my role. My competencies extend beyond timing analysis to include Physical Design and Digital Design, supplemented by adeptness in scripting languages that streamline our processes. My commitment to excellence in semiconductor design is unwavering, as I continue to contribute to Intel's industry-leading innovations.

Location

Greater Bengaluru Area

AI stack

claude code

claude

Work experience

Staff Engineer at Samsung Semiconductor, Nov 2024 - Present · 2 yrs, Bengaluru, Static Timing Analysis and PNR Flow

SoC Design Engineer at Intel Corporation, Jul 2019 - Nov 2024 · 5 yrs 5 mos, Bengaluru, Karnataka, India, Static Timing Analysis in SOC Sub-Full chip Timing : Working on Sub-full chip Static Timing Analysis as a STA Engineer responsible for overall timing closure , quality checks Working on timing Budgeting, constraints cleaning & validation, timing correlations on sub-full chip design. Responsible for the convergence of Caliber at the full-chip level. ECO generation and timing signoff closure on full chip level Handling PNR flow and timing and signoff closure for 2 critical/complex partition : Converged two most complex blocks with instance size of 300K of the latest graphics server project for 10nm/7nm node. Completed the PNR flow starting from floorplan, placement, CTS, Routing using EDA tools IC Compiler II & fusion compiler Worked for timing closure along with other signoff tools (vclp, fev, caliber) for these 2 blocks. Hands on experience in Analog routing and PLL custom requirement in one of the block

Graduate Technical Intern at Intel Corporation, Jul 2018 - Jul 2019 · 1 yr 1 mo, Power Optimization of High-Performance Designs Using Multibit Register Banking: In this project during internship in INTEL , worked on banking of single bit registers into 2bit and 4 bit and Comparing the timing and power and analyzed over all QOR in compile(synthesis flow) and placement stage(PNR flow)

System Engineer at Infosys, May 2015 - Nov 2016 · 1 yr 7 mos, Hyderabad Area, India

Education

Master of Technology - MTech, VLSI Design, Vellore Institute of Technology

Bachelor of Technology (BTech), Electronics and Communication Engineering, Institute Of Technical education and research,bhubaneswar