Headline

Associate Technical Director | Marie Curie Fellow | HW, SW & System Architecture | Extreme HPC & Hard Real-Time Solutions | R&D Proof-of-Concepts | Ex - (CERN, Applied Materials, Xilinx/AMD, Samsung Semiconductor)

About

With over 17 years of cross-functional experience in HW, SW, FPGA and System Architecture, I specialize in solving Extreme HPC, DAQ, and hard realtime challenges. I have a strong track record in leading R&D and Proof of Concept initiatives anticipating technological needs 5-6 years ahead. My experience includes reporting to CXOs, collaborating with subject matter experts, and academic and industry partners to develop innovative, future-ready solutions

Location

Bengaluru

AI stack

gemini

Work experience

Associate Technical Director at Samsung Semiconductor India, Mar 2023 - May 2026 · 3 yrs 3 mos, Bangalore Urban, Karnataka, India, Associate Technical Director @ Samsung Semiconductor India Research

AECG MTS IC Design Engineer at AMD, Feb 2022 - Mar 2023 · 1 yr 2 mos, Hyderabad, Telangana, India

DCG Staff Design Engineer at Xilinx, Jan 2020 - Feb 2022 · 2 yrs 2 mos, Hyderabad, Telangana, India, Worked on Product Planning and Competitive Analysis for Xilinx Data Center Group Benchmarked Xilinx and Competitors solutions for Computational Storage and AI/ML workloads Created containerized apps for Alveo FPGA cards for ease of deployment and use

Senior Technical Lead (HPC Architect) at Applied Materials India, Nov 2018 - Nov 2019 · 1 yr 1 mo, Bangalore, As Primary Member of CTO-HPC group, worked on Custom HPC System Architecture and Algorithm development for Digital manufacturing - Tasked with solving an N+2 problem with Hard real-time (sub 5us) and HPC (~500X speedup over existing accelerated solution) requirements - Successfully developed an innovative and radically new way of solving the problem with theoretically proven linear scaling - Worked towards a Proof of Concept co-developed Hardware, Software solution based on Virtex UltraSCALE+ FPGA containing HBM2 memory and IBM Power 9 processors respectively linked via OpenCAPI interconnect - Wrote a detailed whitepaper on realizing the said system with in depth analysis of compute, memory and bandwidth tradeoffs for different scenarios of requirements, design choices and technology road maps - Initiated and maintained engagements with IBM and OpenCAPI consortium for above purpose

Senior Staff Engineer (Algorithm Developer) at Applied Materials, Aug 2017 - Oct 2018 · 1 yr 3 mos, Bangalore

Education

Doctor of Philosophy (PhD) - All but Dissertation, Reconfigurable Computing and FPGAs, Maynooth University

Master of Science, Electrical and Computer Engineering, University of Florida