---
title: "sowmya rachakonda - Graduate Trainee in Visakhapatnam Rural mandal | Tal"
description: "Meet sowmya rachakonda, actively looking for opportunities in vlsi , VLSI, MTech based in Visakhapatnam Rural mandal. AI stack includes antigravity and codex."
image: "https://tal.club/meet/sowmya-rachakonda/share-image"
---

# sowmya rachakonda on Tal

## Headline

actively looking for opportunities in vlsi , VLSI, MTech

## About

As a Design Verification Engineer at Xeedo Technologies, I applied my skills in Perl, AXI, and APB to verify the functionality and performance of complex system\-on\-chip designs\. I have been working at Xeedo for over a year and a half, and I have contributed to several projects involving low\-power, high\-speed, and mixed\-signal circuits\. I graduated from Vignan Institute of Technology & Sciences with a Bachelor of Technology in Electrical, Electronics and Communications Engineering in 2022, where I learned the fundamentals of digital and analog design, computer architecture, and embedded systems\. I am passionate about designing and testing innovative solutions that meet the needs and expectations of the customers and the industry\. I value teamwork, quality, and continuous learning, and I strive to improve my knowledge and skills in the field of design verification\.

## Location

Visakhapatnam Rural mandal

## AI stack

antigravity

codex

## Work experience

Graduate Trainee at Intel India Private Limited, Jul 2025 \- Present · 1 yr 2 mos, Worked as part of RTL Design team for AI SOCs\. Executed Front\-end design Quality Checks: Clock Domain Crossing \(Enable, Setup Structural Checks\) analysis, RTL Lint to identify and resolve design issues early in the flow\. Basics of UPF and power\-aware design concepts\.

Graduate Technical Intern at Intel Corporation, Jul 2025 \- Jun 2026 · 1 yr, On\-site

Design Verification Engineer at Xeedo Technologies, Jul 2022 \- Jan 2024 · 1 yr 7 mos, Bengaluru, Karnataka, India, During my time at Xeedo Technologies, I worked as an ASIC Design Verification Engineer for a client, Defel Technologies\. My role involved developing and executing testbenches using SystemVerilog and UVM methodologies\. I performed extensive debugging, waveform analysis, and RTL verification activities, which helped ensure the reliability and functionality of the designs\. This experience honed my skills in verification processes and reinforced my understanding of ASIC design\.

Networking Specialist at BSNL, Sep 2020 \- Dec 2020 · 4 mos, I completed a 12\-week internship at BSNL, where I gained foundational knowledge in networking and mobile communication\. This experience allowed me to understand the principles of networking and how they apply to real\-world communication systems\.

## Education

Master of Technology, Electrical, Electronics and Communications Engineering, Amrita Vishwa Vidyapeetham

Bachelor of Technology, Electrical, Electronics and Communications Engineering, Vignan institute of technology and science

[View the original profile](https://tal.club/meet/sowmya-rachakonda)

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