---
title: "Snehul Mistry - Electronics & Communication Engineering Student | Verilog • RTL Design • FPGA • Digital Design | Exploring AI/ML in Ahmedabad | Tal"
description: "Meet Snehul Mistry, Electronics & Communication Engineering Student | Verilog • RTL Design • FPGA • Digital Design | Exploring AI/ML based in Ahmedabad. AI stack includes openai, ChatGPT, and ChatGPT Images. Explore public work links including github."
image: "https://tal.club/meet/snehul-mistry/share-image"
---

# Snehul Mistry on Tal

## Headline

Electronics & Communication Engineering Student \| Verilog • RTL Design • FPGA • Digital Design \| Exploring AI/ML

## About

I'm an Electronics and Communication Engineering student at Parul University with a strong interest in digital design, computer architecture, and semiconductor engineering\. I'm currently building a public portfolio of Verilog RTL projects to strengthen my understanding of hardware design—from basic combinational circuits to processors and FPGA development\. Alongside hardware, I'm also exploring AI/ML and enjoy solving engineering problems through hands\-on projects\. I'm always looking to learn, collaborate, and grow as an engineer\.

## Location

Ahmedabad

## AI stack

openai

ChatGPT

ChatGPT Images

## Education

Bachelor of Technology, Electrical, Electronics and Communications Engineering, Parul University

## Public links

- github: https://github\.com/snehulmistry

[View the original profile](https://tal.club/meet/snehul-mistry)

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