---
title: "SNEHA SHIVANAND KURAGOD - ASIC Physical Design Engineer in Bengaluru | Tal"
description: "Meet SNEHA SHIVANAND KURAGOD, ASIC Physical Design Trainee from RV SKILLS | ICC2 · PrimeTime · STA | 40nm Full-Chip Flow | Low Power & Multi-Voltage Design | BE Electronics | Fresher — Open to Work based in Bengaluru. AI stack includes hugging face, ollama, and openai."
image: "https://tal.club/meet/sneha-shivanand-kuragod/share-image"
---

# SNEHA SHIVANAND KURAGOD on Tal

## Headline

ASIC Physical Design Trainee from RV SKILLS \| ICC2 · PrimeTime · STA \| 40nm Full\-Chip Flow \| Low Power & Multi\-Voltage Design \| BE Electronics \| Fresher — Open to Work

## About

I'm an ASIC Physical Design Engineer with end\-to\-end hands\-on experience implementing a full 40nm chip using Synopsys ICC2 — from floorplanning through signoff\. During my training at RV Skills Design Center, I taped out a complex design with 0\.4M gates across 9 power domains in just 4\.52 mm², meeting a 450 mW power budget with under 5% IR drop\. I personally resolved congestion hotspots, multi\-voltage domain violations, and closed timing across MCMM corners using PrimeTime\. Core skills: • Physical Implementation: Floorplanning, Placement, CTS, Routing, ECOs • Timing: STA, Setup/Hold, MCMM, OCV, CRPR, Constraint Debug • Low Power: UPF, Power Gating, Multi\-Vt, Multi\-VDD, Isolation & Level Shifters • Signoff: DRC, LVS, ERC, Antenna, DFM Tools: Synopsys ICC2, PrimeTime, Virtuoso \| Formats: LEF/DEF, Liberty, SPEF, SDC, TLU\+ I hold a BE in Electronics & Communication \(CGPA 8\.38\) from MVJ College of Engineering and completed an Advanced Diploma in ASIC Design from RV Skills Design Center\. I'm actively seeking full\-time ASIC Physical Design or PnR Engineer roles\. Let's connect\!

## Location

Bengaluru

## AI stack

hugging face

ollama

openai

replit

## Work experience

ASIC Physical Design Engineer at RV Skills Design Centre, Mar 2025 \- Oct 2025 · 8 mos, Bengaluru, Implemented a complete 40nm ASIC physical design flow using Synopsys ICC2, delivering a full\-chip layout of 4\.52 mm² with 0\.4M gates across 9 power domains within a 450 mW budget\. Key contributions: • Led macro placement \(39 macros\), power mesh design, and CTS across multi\-voltage domains • Achieved <5% IR drop; debugged power\-grid DRCs and isolation/level shifter issues • Closed timing across MCMM corners using PrimeTime; resolved setup/hold, OCV, CRPR, and jitter violations • Cleared signoff: DRC, LVS, ERC, antenna checks, redundant via insertion, and constraint debug • Resolved congestion hotspots and cell overlaps to achieve compact, routable floorplan Tools: Synopsys ICC2, PrimeTime \| Formats: LEF, DEF, SPEF, SDC, Liberty, TLU\+

Internship Trainee at Hindustan Aeronautics Limited, Nov 2023 \- Dec 2023 · 2 mos, Karnataka, India, Worked within the Helicopter Avionics and ALH Radio Instruments division at Hindustan Aeronautics Limited \(HAL\)\. • Performed assembly, integration, and testing of electronic avionics subsystems • Conducted troubleshooting and hardware validation of avionics components • Collaborated with cross\-functional engineering teams on subsystem integration

## Education

Bachelor of Engineering \- BE, Electronics and communication engineering, MVJ College of Engineering, Bangalore, India

MATLAB&\#174, MATLAB&\#174, Internshala Trainings

[View the original profile](https://tal.club/meet/sneha-shivanand-kuragod)

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