Headline

IP Lead | MIPI CSI-2 TX/RX Architecture | RTL Design, Synthesis, Lint & CDC @PRSsemicon Technologies

About

I am a Lead Hardware Engineer specializing in the architecture, top-level design, and synthesis of high-performance silicon Intellectual Property (IP), with deep domain expertise in camera interfaces and MIPI protocols (CSI-2 RX). My career is built on driving complex IP components from initial architectural concept through to synthesis, managing high-stakes protocol upgrades, and leading cross-functional engineering teams to deliver enterprise-grade silicon solutions. I excel at translating complex protocol specifications into robust, low-power hardware architectures that integrate seamlessly into complex SoCs. Core Expertise: Protocols & Standards: MIPI CSI-2 (RX), architecture, Advanced Data Formats. Hardware Design & Architecture: RTL Design, Top-Level Integration, Logic Synthesis. Technical Leadership: Team Driving, IP Version Upgrades, Cross-Functional Technical Project Management.

Location

Greater Bengaluru Area

Work experience

Senior Design Engineer at PRSsemicon Technologies (A PRSGroup company), Apr 2026 - Present · 4 mos, Chennai

Design Engineer at PRSsemicon Technologies (A PRSGroup company), Feb 2024 - Mar 2026 · 2 yrs 2 mos, On-site

Design Engineer at PRSsemicon Group (A PRSGroup Company), Aug 2022 - Jan 2024 · 1 yr 6 mos, Chennai

Design Verification Engineer at PRSsemicon Group (A PRSGroup Company), Mar 2022 - Jul 2022 · 5 mos, Chennai

Education

Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering, Acharya

Senior Secondary, PCMB, JSS College for Women, Mysore