---
title: "Sidhant Bhattacharyya - Physical Design Clocking in Greater Bengaluru Area | Tal"
description: "Meet Sidhant Bhattacharyya, GPU Clocking based in Greater Bengaluru Area. AI stack includes claude, gemini, and github copilot."
image: "https://tal.club/meet/sidhant-bhattacharyya/share-image"
---

# Sidhant Bhattacharyya on Tal

## Headline

GPU Clocking

## About

SoC \| EDA \| IP implementation experience across a broad set of products ranging from GPU, Audio DSP's and Radar Accelerators\.

## Location

Greater Bengaluru Area

## AI stack

claude

gemini

github copilot

## Work experience

Physical Design Clocking at Intel Corporation, Jun 2024 \- Present · 2 y 2 mo, Bengaluru, Karnataka, India

Design Engineer at NXP Semiconductors, Jan 2022 \- May 2024 · 2 yrs 5 mos, Delhi NCR, \*RTL logic synthesis, IP evaluation and performance exploration for Radar and DSP systems\. \*SDC generation and co\-development\. \*Bottom\-Up and Top\-Down floorplanning for IP sub\-systems/SoC\. \*APR and downstream Netlist2GDS implementation\. \*TFM evaluations and scriptware utility porting for multi tool usability\. Product lines: Automotive Radar/ Vehicle Control & Network Security Chipsets\. Designs: Cache Coherent NoC, Radar sub\-system\. Certifications: Functional Safety TUV SuD\. Tech Nodes: TSMC 5nm,16ffc\.

Application Engineer at Cadence Design Systems, Sep 2018 \- Jan 2022 · 3 yrs 5 mos, Bengaluru Area, India, \*New Technology Evaluation in collaboration with the RnD code dev team\. \*PPA evaluation of high speed cores\. \*Precision debug of PNR stages during the implementation life cycle\. \*Minimally invasive clock tree design\. \*Flow development and integration of Cadence tech into existing customer CAD flow\. \*Customer information training on the latest implementation methodologies\.

Engineer at Qualcomm, Sep 2015 \- Aug 2018 · 3 yrs, Bengaluru Area, India, Practicing physical design engineer\. Responsibilities included floor planning, PnR and eco implementation of high speed DSP core\. Product Line\- DSP Market Segment\- Mobile Tech nodes\- TSMC\- 7nm/28nm, Samsung\- 8lpp

Intern at Orca Radio Systems, Jan 2015 \- Jul 2015 · 7 mos, Bengaluru Area, India, IC Verification Intern : RTL Verification testbench mixed\-signal IC Technology Node\- 65nm

## Education

Bachelor’s Degree, Electrical, Electronics and Communications Engineering, Manipal institute of technology

Higher Secondary, Science, Bansal classes

[View the original profile](https://tal.club/meet/sidhant-bhattacharyya)

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