---
title: "Siddhant Rohela - Senior Product Manager in Bengaluru | Tal"
description: "Meet Siddhant Rohela, Sr. PM @ ThoughtSpot, IITK, IIMB based in Bengaluru. AI stack includes aistudio, antigravity, and claude code. Explore public work links including github and siddhant-rohela.vercel.app."
image: "https://tal.club/meet/siddhant-rohela/share-image"
---

# Siddhant Rohela on Tal

## Headline

Sr\. PM @ ThoughtSpot, IITK, IIMB

## Location

Bengaluru

## AI stack

aistudio

antigravity

claude code

claude

## Work experience

Senior Product Manager at ThoughtSpot, Aug 2026 \- Present · 1 mo, Bengaluru

Product Manager at ThoughtSpot, Aug 2024 \- Aug 2026 · 2 yrs 1 mo, Bengaluru, Karnataka, India

Product Management Intern at DP World, Apr 2023 \- May 2023 · 2 mos, Bengaluru, Karnataka, India, 1\. Worked on DP World's Supply Chain Visibility Software Solution\. 2\. Performed extensive benchmarking of the firm's offering vis\-a\-vis the rest of the market, identifying key improvement areas in 4 different dimensions\. 3\. Analysed 2 key user personas, quantified the current suitability of the firm's solution w\.r\.t\. each persona\. 4\. Conceptualised the design of a key missing feature, made sure that the competitors' limitations are covered, created a PRD for hand\-off to the development team\.

Analog Design Engineer at Intel Corporation, Mar 2022 \- Jun 2022 · 4 mos, Bengaluru, Karnataka, India, 1\. Designed critical catastrophic trip IP for thermal sensors, reduced simulation time by 98% 2\. Built a modular, fast and precise behavioural circuit model, saving 10\+ days of design time

Analog Design Engineer at Texas Instruments, Jun 2018 \- Jan 2022 · 3 yrs 8 mos, Bengaluru Area, India, 1\. Designed low and mid VIN LDOs in cutting edge BiCMOS & Bipolar Processes\. 2\. Conceptualised a programmable voltage supervisor, now TI standard, boosted functionality per unit area\. 3\. Led 0 to 1 design of flagship project, estimated $2M revenue, de\-risked design in unproven process\. 4\. Created 1st pin\-less scalable Current\-Limit, expanded customer base by 10%, enabled quicker production spins\. 5\. 2 design patents granted\.

Design Engineering Intern at Texas Instruments, May 2017 \- Jul 2017 · 3 mos, Bengaluru Area, India, 1\. Worked on the analysis & selection of error detection schemes for OTP NVM banks\. 2\. Implemented the chosen scheme with the primary product \(LDO\) and completed the design verification of the same\.

## Education

Master of Business Administration \- MBA, Indian Institute of Management Bangalore

Bachelor of Technology \- BTech, Electrical Engineering, Indian Institute of Technology, Kanpur

## Public links

- github: https://github\.com/ciddhant13
- siddhant\-rohela\.vercel\.app: https://siddhant\-rohela\.vercel\.app/

[View the original profile](https://tal.club/meet/siddhant-rohela)

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