Headline

Analog Layout Engineer | Cadence Design Systems

About

As an Analog Layout Engineer with 4 years of experience, my work involves designing high-performance AMS layouts across the industry’s most advanced nodes like TSMC 3nm, 4nm | Samsung 4nm/5nm | Intel 3nm. I have delivered 20+ SERDES layout blocks across 6 tape-outs with DRC/LVS/EMIR sign-off. Proficient in Cadence Virtuoso, Calibre, parasitic optimization, and IP-level reliability verification (ESD, PERC, EMIR).

Location

Bengaluru

AI stack

claude

ChatGPT

Work experience

Design Engineer 1 at Cadence Design Systems, Jul 2023 - Present · 3 yrs 3 mos, Bengaluru, Responsible for end-to-end analog layout delivery from floorplanning and routing to full physical verification, EMIR analysis, and parasitic extraction across multiple technology nodes.

Design Engineering Intern at Cadence Design Systems, Aug 2022 - Jun 2023 · 11 mos, On-site, I built a strong analog layout foundation starting from device physics and fabrication constraints through to full-custom implementation of Op-Amps, LDOs, and VCOs. Gained hands-on experience in precision matching techniques, DRC/LVS verification, metal-fill strategies, and noise isolation transforming classroom knowledge into practical, silicon-ready layout skills.

Education

Bachelor of Engineering - BE, Electronics and Communications Engineering, Jawaharlal Nehru national college of engineering