Headline

Design Verification Trainee @ChipEdge | System Verilog | UVM | AMBA (APB, AHB, AXI) | Functional & Coverage-Driven Verification | Electronics & Telecommunication Engineer |

About

• Understanding of digital design concepts, SoC architecture, and verification methodologies. • Familiar with verification using System Verilog and UVM, including testbench development, stimulus generation, functional coverage, virtual sequences, sequencer connections, functional coverage, and debugging. and debugging. • Hands-on experience with simulation tools (Synopsys VCS) and verification of standard bus protocols like AMBA (APB, AHB, AXI) through project work. • Collaborated on projects involving testbench creation, analysis of design requirements, and implementation of verification strategies. • Enthusiastic about front-end VLSI design and verification, with a passion for exploring digital design and ensuring functional correctness through verification techniques.

Location

Bengaluru

AI stack

openai

Work experience

Design Verification Trainee at ChipEdge, Jun 2025 - Present · 1 yr 4 mos, Worked on front-end design verification using System Verilog and UVM. Involved in building testbench components, writing sequences, and verifying AMBA-based designs through simulation, coverage, and debugging.

Graphics Mentor at TPC-PCE, Sep 2024 - May 2025 · 9 mos

Graphics Head at TPC-PCE, Sep 2023 - Sep 2024 · 1 yr 1 mo

Graphics Co-ordinator at TPC-PCE, Sep 2022 - Aug 2023 · 1 yr

Education

Bachelor of Technology - BTech, Electronics and telecommunication, Pillai College of Engineering

Science, St. Xaviers english high school and Jr. College