---
title: "Shreyansh Vajpayee - HW Verification Engineer in Bengaluru | Tal"
description: "Meet Shreyansh Vajpayee, Design Verification Engineer | AXI/APB Protocol | SystemVerilog | Functional Coverage & Constraints | Python Automation | Silicon Tapeout Readiness based in Bengaluru. AI stack includes claude code, gemini, and openai."
image: "https://tal.club/meet/shreyansh-vajpayee/share-image"
---

# Shreyansh Vajpayee on Tal

## Headline

Design Verification Engineer \| AXI/APB Protocol \| SystemVerilog \| Functional Coverage & Constraints \| Python Automation \| Silicon Tapeout Readiness

## About

Design Verification Engineer with hands\-on experience in pre\-silicon verification of processor\-class IPs and on\-chip protocols such as AXI and APB\. My work focuses on: • Developing SystemVerilog functional coverage models \(covergroups, crosses, bins, illegal/ignore bins\) • Writing targeted constraints to hit corner\-case scenarios • Debugging complex protocol, alignment, burst, and legality issues • Driving coverage closure to tapeout\-quality signoff • Building Python\-based automation frameworks for scalable regression analysis At Baya Systems, I am responsible for verification signoff readiness, achieving 100% functional and code coverage across multiple IP regressions and ensuring silicon\-quality validation\.

## Location

Bengaluru

## AI stack

claude code

gemini

openai

## Work experience

HW Verification Engineer at Baya Systems, Jun 2025 \- Present · 1 yr 4 mos, Bengaluru, Design Verification Engineer – Baya Systems • Developed SystemVerilog functional coverage models for on\-chip protocols including AXI and APB • Wrote targeted constraints to drive corner\-case scenarios and accelerate coverage closure • Designed and implemented an exclusion\-aware coverage automation framework for scalable regression analysis \(mergevdb/URG\) • Automated parameter extraction using Python\-based flows to ensure configuration\-consistent verification • Debugged protocol alignment, burst\-type, and legality issues through waveform analysis and constraint tuning • Drove verification signoff readiness, achieving 100% functional and code coverage for silicon tapeout

## Education

Master of Technology \- MTech, VLSI & ES, Indraprastha Institute of Information Technology, Delhi

Bachelor of Technology \- BTech, Electronics and Communication Engineering, University Institute of Technology, RGPV

[View the original profile](https://tal.club/meet/shreyansh-vajpayee)

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