Headline

VLSI Design & Verification Trainee | RTL Design (Verilog, SystemVerilog) | Functional Verification | UVM | Digital Design | ASIC/SoC | Trained Fresher | Semiconductor Technology

About

During this journey, I gained strong knowledge in RTL Design, Verilog/SystemVerilog, Functional Verification, and UVM fundamentals. I also worked on concepts like Finite State Machines (FSM), Assertions, Coverage Analysis, and Testbench development. This experience helped me strengthen my understanding of the ASIC design flow and enhanced my practical skills using industry tools. I am now eager to apply my knowledge and explore opportunities in VLSI Design and Verification.

Location

Bengaluru

AI stack

aistudio

gemini

hugging face

openai

Work experience

Design and Verification Trainee at Maven Silicon, May 2025 - Present · 1 yr 1 mo, Bengaluru, Completed an industry-oriented training program in Advanced VLSI Design and Verification at Maven Silicon, gaining strong knowledge in both RTL design and functional verification methodologies. The course covered key concepts including Verilog and SystemVerilog programming, RTL design, finite state machines (FSMs), combinational and sequential circuit design, and testbench development. Acquired hands-on experience in functional verification, including assertion-based verification, coverage-driven verification, and fundamentals of UVM (Universal Verification Methodology). Worked on real-time projects like AXI interconnect and Router 1×3 involving design and verification of digital blocks, developing skills in debugging, simulation, and waveform analysis using industry-standard EDA tools. This training enhanced my understanding of the ASIC design flow, from specification to verification, and prepared me for roles in VLSI design and verification engineering.

Design Verification intern at Logic Cells Technologies, Feb 2025 - May 2025 · 4 mos, Bengaluru, Designed and verified a FIFO (First-In First-Out) architecture using Verilog, implementing efficient read/write pointer logic and handling full/empty conditions. Developed a robust testbench in SystemVerilog to validate functionality, including edge cases like overflow and underflow. Performed functional verification and waveform analysis, ensuring data integrity and correct sequential behavior across all test scenarios.

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, KLE Institute of Technology, HUBLI