Headline

Physical Design Engineer | VLSI Backend | Synopsys ICC2 | Floorplanning • CTS • STA | Seeking Full-Time Opportunity

About

Entry-level Physical Design Engineer focused on ASIC Backend VLSI and RTL-to-GDSII implementation. Currently training at Takshila VLSI, Bengaluru, with hands-on exposure to block-level physical design flow using Synopsys ICC2, Cadence Innovus and Synopsys PrimeTime. Project exposure includes floorplanning, power planning, macro placement, placement optimization, Clock Tree Synthesis, global routing, detailed routing, Static Timing Analysis, setup and hold analysis, timing closure, DRC and LVS concepts, and sign-off quality checks. Completed a block-level Raven Wrapper physical design project in 45nm, covering floorplanning, placement, CTS, routing and post-route timing analysis concepts. Comfortable reading timing reports, understanding skew and latency, analyzing congestion, and working with backend implementation flow fundamentals. Tools and keywords: ICC2, Innovus, PrimeTime, STA, CTS, PnR, Routing, Timing Closure, Floorplanning, Macro Placement, DRC, LVS, TCL Basics, Linux. Actively looking for Physical Design Engineer Trainee, Backend VLSI Trainee, ASIC Physical Design Intern, STA Intern or Graduate Engineer Trainee roles in Bengaluru, hybrid or remote.

Location

Bengaluru

Work experience

Physical Design Engineer Trainee at Takshila Institute of VLSI Technologies, Nov 2025 - Present · 9 mos, Bengaluru, Undergoing intensive VLSI Physical Design training with hands-on project implementation using Synopsys ICC2. • Executed end-to-end ASIC Physical Design flow: Floorplanning → Placement → CTS → Routing → STA • Worked with technology libraries, netlists, SDC constraints across 32nm and 45nm nodes • Performed congestion analysis, timing analysis, and design QoR evaluation • Gained exposure to STA, MMMC concepts, setup/hold timing analysis using PrimeTime • Generated and analyzed utilization, congestion, timing, CTS, and routing reports • Developed TCL scripting skills for Physical Design automation in Linux environment Projects: ORCA TOP (32nm, 52K+ cells) | Raven Wrapper (45nm)

Education

Class XII, cbse

Class X, cbse