Headline

Engineer 1@ Prajna | Design Verification Engineer

About

I am an energetic and ambitious person who has developed a mature and accountable approach to any task I undertake, or the situation I face. I look forward to better opportunities to explore and expand my skills and grow . I look forward to a challenging position as an engineer to utilize my analytical skills and ability to work well with others. Succeed in an environment of growth and excellence by being motivated and hard working.

Location

Hyderabad

AI stack

claude

Work experience

Engineer 1 at prajna semiconductor pvt ltd, Apr 2026 - Present · 7 mos, Hyderabad

Engineer 1 at Soctronics, Dec 2024 - Mar 2026 · 1 yr 4 mos, Design Verification Engineer

Engineer Trainee at Soctronics, Dec 2023 - Nov 2024 · 1 yr, Hyderabad, Telangana, India, Logic Design and Verification Engineer

Design Verification Engineer Trainee at AMD VEDA IIT, Sep 2022 - Nov 2023 · 1 yr 3 mos, Hyderabad, Telangana, India, Learned varius concept of vlsi designing and gained the advance knowledge of design verification using scripting and varius procedural programming languages .

President at Dinobots-KIET, Apr 2021 - May 2023 · 2 yrs 2 mos, Kiet group of institutions ghaziabad, I had managed all the activities in club and worked as an electronic and embedded system designer.

Education

Master of Technology (M.Tech), VLSI Design and Microelectronics, Birla Institute of Technology and Science, Pilani

Bachelor of Technology - BTech, Electronics and Communications Engineering, kiet group of institutions