---
title: "ShivaKumar Ravula - R&D Engineer in Bengaluru | Tal"
description: "Meet ShivaKumar Ravula, R&D Engineer @Synopsys Inc | C/C++ • GPU Acceleration (CUDA) | Linux | Arch64/Arm64 porting •EDA | Performance Engineering based in Bengaluru. AI stack includes codex, cursor, and opencode."
image: "https://tal.club/meet/shivakumar-ravula/share-image"
---

# ShivaKumar Ravula on Tal

## Headline

R&D Engineer @Synopsys Inc \| C/C\+\+ • GPU Acceleration \(CUDA\) \| Linux \| Arch64/Arm64 porting •EDA \| Performance Engineering

## About

I'm a Performance & Platform Engineer at Synopsys, where I work at the intersection of systems software, GPU computing, and cross\-platform engineering on enterprise\-grade EDA tools\. My current focus areas: ▸ GPU Acceleration — Profiling CPU bottlenecks in Synopsys EDA tools and offloading compute\-intensive workloads to GPU using CUDA, achieving measurable runtime improvements on large\-scale designs\. ▸ AArch64 / ARM64 Porting — Porting production Linux64 software to AArch64 and PPC64 platforms, resolving architecture\-specific compiler, alignment, and SIMD issues\. ▸ Performance Engineering — Runtime profiling, bottleneck analysis, and optimization of core EDA components including nSchemaDB generation\. ▸ Platform Reliability — End\-to\-end ownership of build pipelines, regression infrastructure, and cross\-compiler validation \(GCC, Clang\) across platforms\. I graduated with a B\.Tech in Computer Science from IIIT Srikakulam \(2023\) and have been building deep expertise in C/C\+\+, systems programming, and low\-level performance optimization since then\.

## Location

Bengaluru

## AI stack

codex

cursor

opencode

## Work experience

R&D Engineer at Synopsys Inc, Nov 2024 \- Present · 1 yr 10 mos, Bengaluru, GPU Acceleration: Identified and profiled CPU bottlenecks in core EDA tool components; offloaded compute\-intensive workloads to GPU \(CUDA\), delivering measurable runtime improvements on large\-scale design verification workflows\. AArch64 Platform Porting: Ported production Linux x86\-64 software to AArch64 and PPC64 targets, resolving architecture\-specific compiler, alignment, SIMD, and endianness issues across GCC and Clang toolchains\. Performance Optimization: Profiled and optimized runtime performance of nSchemaDB generation pipeline, reducing processing overhead through algorithmic improvements and cache\-aware data access patterns\. Build & Regression Infrastructure: Maintained cross\-platform build pipelines and regression suites; diagnosed and resolved daily build failures, test regressions, and runtime defects across multiple product branches\. Compiler Validation: Ensured compiler compatibility across platforms \(GCC, Clang\) and validated correct executable generation for ARM64 and PPC64 targets in CI/CD workflows

R&D Intern, Synopsys at Synopsys Inc, Mar 2024 \- Nov 2024 · 9 mos, Noida, Tool Enhancement \(VC Static\): Extended the VC Static analysis tool to support VHDL shift operators, expanding language coverage and improving utility for hardware verification engineers\. GUI Defect Resolution: Diagnosed and fixed rendering defects in the NativeGUI property panel — corrected display of isolation strategies for scalar objects and implemented navigational links to the UPF Browser, improving usability for design engineers\. Performance Debugging: Contributed to runtime performance improvements and resolved build, regression, and runtime defects as part of day\-to\-day debugging on a large\-scale C\+\+ EDA codebase\.

DSA Tecnical Mentor at FACE Prep, Aug 2023 \- Dec 2023 · 5 mos, Coimbatore, Tamil Nadu, India, 1\) Conducted training sessions on Data Structures and Algorithms for students\. 2\) Guided and supported students in securing placements successfully\.

## Education

Bachelor of Technology \- BTech, Computer Science, RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, SRIKAKULAM

PUC, MPC, RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, SRIKAKULAM

[View the original profile](https://tal.club/meet/shivakumar-ravula)

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