Physical Design Engineer @ L&T Semiconductor Technologies | VLSI Design, Signal Processing

Bengaluru, Karnataka, India

Bengaluru, Karnataka, India
India

Uttar Pradesh, India

New Delhi, Delhi, India







Master of Technology - MTech, Vlsi design
Vellore Institute of Technology

B.tech, Electrical and Electronics Engineering
SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGINEERING AND MANAGEMENT, LUCKNOW
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As a passionate and skilled VLSI Engineer, I am dedicated to advancing the field of semiconductor design through hands-on experience and continuous learning. With a solid foundation in Physical Design, Post-Silicon Validation, and automation, I specialize in RTL design, Verilog, FPGA programming, and hardware description languages. My technical expertise is complemented by proficiency in EDA tools such as Xilinx Vivado, ModelSim, and Synopsys Suite, enabling me to optimize designs for area, power, and performance. Currently working as a Physical Design Engineer at L&T Semiconductor Technologies, I focus on floorplanning, placement, routing, and timing closure to ensure successful chip design implementation. In my previous role as a Student Technical Intern at NXP Semiconductors, I contributed to automating workflows and developing test cases for safety-critical IPs, significantly reducing process times. My academic background includes a Master's in VLSI Design from VIT Vellore, where I also earned recognition for academic excellence. I’m always looking to expand my knowledge and contribute to the semiconductor industry's growth through innovation and collaboration. Feel free to connect if you're interested in discussing VLSI design, automation, or the future of semiconductor technology.
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Physical Design Engineer(PDN , EMIR sign off,PNR, STA) at L&T Semiconductor Technologies, Jul 2024 - Present · 2 yrs 3 mos, Bengaluru, Karnataka, India
Technical Intern at NXP Semiconductors, Sep 2023 - Jun 2024 · 10 mos, Bengaluru, Karnataka, India
Subject Matter Expert at Coursehero, May 2021 - Feb 2022 · 10 mos, India
Q/A expert at Chegg Inc., Mar 2019 - Mar 2022 · 3 yrs 1 mo, Uttar Pradesh, India
Research Intern at Alasa Electronics, Oct 2017 - May 2018 · 8 mos, New Delhi, Delhi, India, worked in research and development (power/ev) division
Master of Technology - MTech, Vlsi design, Vellore Institute of Technology
B.tech, Electrical and Electronics Engineering, SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGINEERING AND MANAGEMENT, LUCKNOW