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SoC Methodology

About

SoC Methodology: - AI-based Design Experience (AIDE) - Agentic flow for root-cause-analysis for debug, coverage reachability analysis - Agentic flow to optimize test scenario setup/analysis to overcome sv randomization license bloat - Agentic flow to create consisitent UVM code - Streamline RTL design using Python based design entry - Simplify CI/CD for CAD Flow - Standardize UVM architecture for consisitency, reuse and automation with AI - Guide overall methodology around design/verification - CSR automation, performance analysis, model-driven system design ASIC/FPGA Flow Projects: - Analyze ASIC project requirements, provide specific design/verification methodology guidance and one-on-one tool flow deployment consultation with the focus on extensible Digital Design Verification flow. - Lead, manage and deploy Advanced Functional Verification and Formal Verification Flows using SystemVerilog/UVM/SVA at mil-aero and other IC companies including migration to TBX testbench acceleration emulation systems. - Provide custom solutions for • migrating Vera to UVM, • integrating MATLAB into UVM, • integrating SystemC into UVM, • Python based UVM Register code automation, • reduce UVM-based runtimes using check-points... - Published various articles that are currently used by the customers: • A Scalable Approach for TLM across SystemC and SystemVerilog • Planning SystemVerilog Adoption • Polymorphic Interfaces: An Alternative for SystemVerilog Interfaces • DVCON 2015: UVM Sans UVM: An approach to automating UVM testbench writing • DVCON 2015: Goldilocks and System Performance Modeling: A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology Software Development Projects: Lead, Design and Implement integrating various 3rd party tools with ADS (Advanced Design Systems - an Analog/RF/DSP System Design Tool from Agilent EEsof). - Allow HDL models by integrating with HDL Simulators (ModelSim/QuestaSim/NCSim/VCS) - using different IPC strategies on Unix/Linux/Windows - Allow DSP software by integrating with TI ISS for TMS320C6X, TMS320C54X, TMS320C55X, etc. via COM API to control the simulation, access/read/write the DSP memory, etc. - Allow SystemC models by integrating OSCI SystemC - Integrate ADS Analog/RF/DSP content into Cadence AMS Designer. This project involved GUI work in two different tools: ADS and Cadence AMSD (DFII). - Integrate ADS simulator and data display tools into Cadence Analog Artist as RFDE (RF Design Environment) using Cadence OASIS environment and MPS (Multi Process Skill).

Location

Oak Park

Work experience

SoC Methodology at Meta, May 2020 - Present · 6 yrs 2 mos, - AI-based Design Experience (AIDE) - Agentic flow for root-cause-analysis for debug, coverage reachability analysis - Agentic flow to optimize test scenario setup/analysis to overcome sv randomization license bloat - Agentic flow to create consisitent UVM code - Streamline RTL design using Python based design entry - Simplify CI/CD for CAD Flow - Standardize UVM architecture for consisitency, reuse and automation with AI - Guide overall methodology around design/verification - CSR automation, performance analysis, model-driven system design

Sr Staff Apps Consultant at Synopsys Inc, May 2016 - May 2020 · 4 yrs 1 mo, Greater Los Angeles Area, Architect, Develop and Deploy ASIC/FPGA Design Verification Flows.

Applications Engineering Consultant, Functional Verification at Mentor Graphics, Apr 2006 - May 2016 · 10 yrs 2 mos, Architect, Lead, Manage and Deploy Advanced Functional Verification and Formal Verification Flows using SystemVerilo/UVM/SVA Architect, Develop and Deploy onsite Functional Verification flows for ASIC/FPGA designs using: - UVM block-to-system verification - Standard bus protocol Verification IP - Static CDC Analysis - SystemVerilog Assertion based Formal Analysis - HW/SW Co-verification - MATLAB/C/SystemC with UVM - Testbench Acceleration with Emulators Activities: - Analyze customer issues and guide flow setup with goals to rampup deployment - Provide ad hoc training and software solutions such as: • migrating Vera to UVM, • integrating MATLAB into UVM, • integrating SystemC into UVM, • Python based UVM Register code automation, • reduce UVM-based runtimes using check-points, • etc. - Work closely with Engineering • Initial decision making process and beta bashing of AVM/OVM/UVM • To provide different inputs including working prototypes for UVM Debugging, UVM Register code creation and debugging, Assertion Automation, etc. • Provided collaterals to be deployed at various other sales engagements, internal training - Work with Sales teams on business planning, strategy decisions, tactics execution • Uncovered various opportunities in accounts where Mentor had no presence • Position Mentor solutions depending on customer situations either to work with their current flow or migrate - Member of Accelera’s Mixed Language Working Group (MLWG) • Involved in the extension of SystemVerilog UVM to other languages such as C/C++/MATLAB/SystemC - Published various articles: • A Scalable Approach for TLM across SystemC and SystemVerilog • Planning SystemVerilog Adoption • Polymorphic Interfaces: An Alternative for SystemVerilog Interfaces • DVCON 2015: UVM Sans UVM: An approach to automating UVM testbench writing • DVCON 2015: Goldilocks and System Performance Modeling: A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology

Software Design Engineer at Hewlett Packard, Agilent Technologies, Jan 1998 - Feb 2006 · 8 yrs 2 mos, Greater Los Angeles Area, - Conduct new product investigations and development in system design aspect of the ADS tool set using Ptolemy (C++ class library for System Designs). - Created an interface to embed the system design as part of any other third party tool. This involved providing a C++ API for users to access input/output of ADS schematic. - Investigate different approaches for Analog Mixed Signal (AMS) simulation architectures. This investigation involved looking at architectures for integrating Digital IP with our A/RF simulations and performing a seamless data transfers between the two. The simulation semantics issues required to be sorted out across the two different simulation environments. - Key architect for the revolutionary RFDE Wireless Test Benches, Sources and Expressions that make the System Design Tool available for RFIC Engineers for wireless measurements. This was a new concept developed to help RFIC developers to not just do traditional measurements but also wireless measurements.

Software Design Engineer at Texas Instruments, Jan 1995 - Aug 1996 · 1 yr 8 mos, Bengaluru Area, India, Designed Hardware/Software simulator for the TMS320C6X DSP. Developed the simulator accessible in a VHDL environment by writing a C wrapper so that VHDL modules could talk to the DSP core written in C++.

Education

Masters of Science, Electrical Engineering, The University of Tulsa

BE, Electronics, shivaji university