Headline

SOC/ASIC/RTL/FPGA Design and Emulation Prototype engineer "Impossible is my favourite starting point"

About

I am an experienced SOC (System-on-Chip) Design Engineer with 10+ years of expertise. I excel in SOC architecture, RTL design (Verilog/SystemVerilog), ASIC/FPGA design, and robust verification. My skills include firmware development, low-power design, simulation/emulation, and cross-functional collaboration. I manage projects effectively, ensuring on-time deliveries. Proficient in analog/digital circuit design, IP integration, debugging, scripting (Python/Perl), and SystemVerilog/VHDL. I'm well-versed in embedded processors, clock/power management, and industry standards. Continuous learning, problem-solving, and meticulous documentation are integral to my approach. I prioritize compliance, security, and safety, making me a valuable asset to SOC design teams, delivering cutting-edge solutions. SOC Architecture: I possess a deep understanding of SOC architecture, allowing me to seamlessly integrate various IP blocks, memory subsystems, and peripherals to create cohesive, high-performance solutions. RTL Design: My proficiency in RTL (Register Transfer Level) design using Verilog and SystemVerilog ensures robust and efficient hardware implementations. ASIC and FPGA Design: I excel in ASIC and FPGA design methodologies, from the initial concept to the final tape-out or bitstream generation, delivering reliable and high-performance chips. Firmware Development: My experience extends to firmware and embedded software development, enabling smooth hardware-software co-design and functionality. Low Power Design: I am well-versed in low-power design techniques, ensuring optimal power efficiency while meeting performance targets in SOC designs. Simulation and Emulation: Proficiency in industry-standard simulation tools and emulation platforms allows me to perform pre-silicon validation and performance analysis efficiently. Cross-functional Collaboration: Effective communication and teamwork skills enable me to collaborate seamlessly with hardware engineers, software developers, and system architects to drive projects to successful outcomes. IP Integration: I have successfully integrated third-party IP cores and custom IP blocks into SOC designs, enhancing functionality and reducing development time. Debugging Skills: Strong debugging skills enable me to quickly identify and resolve hardware and software issues during SOC development, minimizing project delays. Scripting and Automation: Proficiency in scripting languages like Python and Perl facilitates automation, streamlining design and verification tasks for increased efficiency.

Location

Bengaluru

AI stack

codex

Work experience

SoC Design Engineer at Synopsys Inc, Aug 2022 - Present · 4 yrs 2 mos

Staff Engineer soc design at Synopsys Inc, Aug 2022 - Present · 4 yrs 2 mos

RTL Design engineer at Capegemini Consulting India Private Limited at Capgemini Engineering, Jun 2018 - Aug 2022 · 4 yrs 3 mos, Bangalore Urban, Karnataka, India

RTL Design Engineer at Space Applications Centre, ISRO, Jun 2017 - Apr 2018 · 11 mos, Ahmedabad, Gujarat, India, Indian Space Research Organization (ISRO) : Design of A High Throughput & Efficient FPGA Implementation of Hyper-spectral and Multispectral Compressor by using CCSDS standard 123 for Space Satellite Nature of project: Design an efficient compression of hyperspectral images on-board satellites is mandatory in current and future space missions in order to save bandwidth and storage space. Reducing the data volume in space is a challenge that has been faced with a twofold approach: to propose new highly efficient compression algorithms; and to present technologies and strategies to execute the compression in the hardware available on-board. The Consultative Committee for Space Data Systems (CCSDS), a consortium of the major space agencies in the world, has recently issued the CCSDS 123 standard for multispectral and hyperspectral image (MHI) compression, with the aim of facilitating the inclusion of on-board compression on satellites by the space industry.  Start Date: June-2017 End Date: April 2018 Duration: Approx. 1 Yr.  Objectives  Involved in development of Design of RTL code in VHDL language for full algorithm.  Involved in development of Test bench for functionality and mathematical calculation verification.  Involved in development of equivalent MATLAB Simulink model to dump the data for comparison with RTL design.  Involved in development of system specification document and system design document.  Involved in Test Plan Development, Test Bench Development, Test Simulation and Analysis, GLS setup, Debug and Code & Functional Coverage Analysis.  Technical Skills Required  Platform : Linux, Windows  HDL : VHDL  Scripting Languages : Perl  Protocols : UART  Tools : Xilinx ISE, Modelsim, QuestaSim, Matlab Simulink  Standards : CCSDS 123 standard

Project assitant at Indian Institute of Technology, Bombay, Jan 2015 - Apr 2016 · 1 yr 4 mos, Mumbai, Maharashtra, India, FPGA-based Accelerators of Deep Learning Networks Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged, and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolution neural networks (CNNs) have demonstrated their effectiveness in image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve desired performance levels. Consequently, hardware accelerators that use application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and graphic processing units (GPUs) have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism as well as due to their energy efficiency. we review recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in recent trends in FPGA-based accelerators of deep learning networks. Thus, this review is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

RTL design engineer at five core electronics ltd ,delhi, Aug 2013 - Dec 2014 · 1 yr 5 mos, Greater Delhi Area, Five Core Electronics Ltd, Delhi-: Design of Image Edge detection system using sobel filter algorithm in FPGA. Nature of project: Design an efficient Edge detection is one of the important stages in image processing. The Sobel edge detection algorithm is the most widely used edge detection algorithm due to Characteristics. The software is implemented using MATLAB, also the Sobel edge detection algorithm is implemented and presented on Spartan3E (XC3S1600E) FPGA by ISE12.1. This project mainly used the Sobel operator method to do edge detection processing on the normal scale images. It has been proven by the results we have obtained that the edge detection mathematical method using MATLAB software and FPGA is very good in the analysing the image and the results reach to 99%. A 256×256 size input image is used in this work.  Start Date: Aug-2013 End Date: December 2014 Duration: Approx. 1.5 Yr.  Objectives  Involved in development of Design of RTL code in VHDL language for full algorithm.  Involved in development of Test bench for functionality and mathematical calculation verification.  Involved in verification of equivalent MATLAB model to dump the data for comparison with RTL design.  Involved in development of system specification document and system design document.  Involved in Test Plan Development, Test Bench Development, Test Simulation and Analysis, GLS setup, Debug and Code & Functional Coverage Analysis.  Technical Skills Required  Platform : Linux, Windows  HDL : VHDL  Protocols : UART  Tools : Xilinx ISE, Modelsim, QuestaSim, Matlab Simulink  Standards : Sobel filter algorithm

Education

Master of Technology - MTech, Electrical, Electronics and Communications Engineering, Pondicherry University

B.E, Electrical, Electronics and Communications Engineering, North Maharashtra University