Headline

Senior Design Verification Engineer at Mirafra Technologies @ AMD Client

About

Hi, I am Shaik. Senior Design Verification Engineer with 4+ years of experience in SoC/IP verification using SystemVerilog and UVM. Experienced in developing reusable UVM-based verification environments, creating verification plans and testcases, debugging RTL and simulation issues, performing regression analysis, and driving functional and code coverage closure. Hands-on experience in verifying NoC (Network-on-Chip) architectures and AMBA protocols including AXI and APB. Proficient in SystemVerilog, UVM, Assertions (SVA), verification planning, coverage analysis, and debugging using Synopsys VCS and Verdi. Strong collaborator with cross-functional design teams, committed to delivering high-quality and reliable silicon solutions.

Location

Hyderabad

Work experience

Senior Design Verification Engineer at Mirafra Technologies, Apr 2025 - Present · 1 yr 4 mos

Verification Engineer 2 at Mirafra Technologies, Jul 2023 - May 2025 · 1 yr 11 mos, Hyderabad, Telangana, India

Verification Engineer 1 at Mirafra Technologies, Apr 2022 - Jun 2023 · 1 yr 3 mos, Hyderabad, Telangana, India

Education

Master of Technology - MTech, VLSI, kl university

Bachelor's degree, Electrical, Electronics and Communications Engineering, VIGNAN NIRULA OF INSTITUTE OF TECH AND SCI FOR WOMEN