---
title: "Sekar P - Signal Integrity Engineer in Bengaluru | Tal"
description: "Meet Sekar P, Signal Integrity Engineer | HSIO Validation | PCIe · DDR5 · USB | Post-Silicon Testing & Python Automation | Working on NVIDIA GPU Platforms | L&T Technology Services based in Bengaluru."
image: "https://tal.club/meet/sekar-p/share-image"
---

# Sekar P on Tal

## Headline

Signal Integrity Engineer \| HSIO Validation \| PCIe · DDR5 · USB \| Post\-Silicon Testing & Python Automation \| Working on NVIDIA GPU Platforms \| L&T Technology Services

## About

Signal Integrity and HSIO Validation Engineer with 2\+ years of experience in post\-silicon validation of high\-speed interfaces, currently working on NVIDIA GPU platform programs at L&T Technology Services\. My core focus is ensuring the electrical integrity of high\-speed I/O interfaces — PCIe, USB, and DDR — from silicon bring\-up through production sign\-off\. I work at the intersection of hardware validation, lab characterization, and test automation: developing Python\-based frameworks that streamline test execution, reduce manual effort, and improve signal coverage across interfaces\. What I work on: • Post\-silicon electrical validation of HSIO interfaces \(PCIe, USB, DDR\) • Lab characterization using high\-speed equipment — oscilloscopes, BERTs, protocol analyzers • Eye diagram analysis, jitter measurement, and margin analysis for interface compliance • Python automation for test sequencing, data parsing, and reporting • Test plan development and compliance testing against industry standards \(PCIe, JEDEC\) • Cross\-functional collaboration with circuit design, board design, and firmware teams I have a strong foundation in Electrical and Electronics Engineering \(Sri Sai Ram Institute of Technology, 2024\) and hold cloud computing certifications from edX\. I'm continuously building depth in SI/PI simulation tools and high\-speed protocol standards\. Open to connecting with signal integrity professionals, hardware validation engineers, and ER&D teams working on next\-generation computing platforms\. 📍 Bengaluru \| 📧 sekarsiva2007@gmail\.com

## Location

Bengaluru

## Work experience

Signal Integrity Engineer at L&T Technology Services, Dec 2024 \- Present · 1 yr 9 mos, Bengaluru, Karnataka, India, • Validate HSIO interfaces \(PCIe Gen5, USB 3\.x, DDR4/5\) on NVIDIA GPU platforms, executing test plans covering electrical compliance, margin analysis, and eye diagram characterization • Develop Python automation scripts for test sequencing and data logging, significantly reducing manual test execution time • Operate lab equipment including high\-speed oscilloscopes, BERTs, and protocol analyzers to characterize SI performance and root\-cause link failures • Collaborate with circuit design, board design, and firmware teams to resolve HSIO bring\-up issues and optimize interface performance • Author and maintain test documentation including test plans, test reports, and bug reports aligned with PCIe and JEDEC compliance standards

Associate Engineer Trainee at L&T Technology Services, Sep 2024 \- Nov 2024 · 3 mos, Chennai, Tamil Nadu, India, Onboarding and technical training in SI/PI fundamentals, high\-speed interface protocols, and hardware validation methodologies\.

Summer Intern at Yokogawa India Limited, Jun 2023 \- Jul 2023 · 2 mos, Bengaluru, Karnataka, India, Gained exposure to industrial instrumentation systems and electrical measurement equipment\. Observed testing and calibration workflows in a professional engineering environment\.

Summer Intern at GH Induction India Pvt Ltd, Jul 2022 \- Jul 2022 · 1 mo, Chennai, Tamil Nadu, India, Gained brief exposure to induction heating equipment and industrial electrical systems

## Education

Bachelor of Engineering \- BE, Electrical and Electronics Engineering, Sri Sai Ram Institute of Technology \(Sairam Group of Institutions\)

[View the original profile](https://tal.club/meet/sekar-p)

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